Samsung Electronics Co., Ltd.

Other

Jae-Yong Jeong

Chi-Weon Yoon

Sung-Soo Lee

Heung-Soo Lim

Ki-Tae Park

Jin-Young Chun

Sang-Soo Park

Bo-Geun Kim

Kee-Ho Jung

Young-Ho Lim

Hyun-Jin Kim

Jung-Woo Lee

Myung-Hoon Choi

Byung-Hoon Jeong

Young-Don Choi

Jeong-Don Ihm

Yong-Kyu Lee

Kye-Hyun Kyung

Chul-Ho Lee

Kui-Yon Mun

Seok-cheon Kwon

Min-Jae Lee

Sung-Kyu Park

Chung-Ho Yu

Soo-Han Kim

Heung-soo Lim

Sang-Lok Kim

Tae-Sung Lee

Jae-phil Kong

In-Mo Kim

Young-Seok Hong

Seung-Hun Choi

Hyun-Jun Yoon

Sang-Wan Nam

Tae-young Kim

Tae-Hyun Kim

Jong-Min Kim

Bum-Soo Kim

Min-Seok Kim

Jae-Woo Park

Beomkyu Shin

Ji-Hyun In

Dong-hee Lee

Dong-kyo Shim

Soo-Woong Lee

Wan-Dong Kim

Beom-Kyu Shin

Sang-Lyul Min

Sam-hyuk Noh

Yoo-kun Cho

Jin-Seon Yeom

Je-Sung Kim

Jae-Phil Kong

Gui-Young Lee

Myoung-Hoon Choi

Jong-Moo Choi

A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

Nonvolatile memory devices including memory planes and memory systems including the same

A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Defect detection structure of a semiconductor die, semiconductor device including the same and method of detecting defects in semiconductor die

A method of controlling a first memory controller that controls a non-volatile memory device includes: the first memory controller receiving first data and a first physical address from a second memory controller via a first interface of the first memory controller; the first memory controller storing the first data in a non-volatile memory buffer of the first memory controller; and the first memory controller programming the first data stored in the non-volatile memory buffer in a first physical region of the non-volatile memory device corresponding to the first physical address.

Method of operating memory controller and memory system, and the memory system

A non-volatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit, and a control logic circuit. The page buffer circuit includes a plurality of first page buffers and a plurality of second page buffers, each including a sense latch, a data latch, and a cache latch. The sense latch senses data stored in the memory cell array and dumps the sensed data to the data latch, the data latch dumps the data dumped by the sense latch to the cache latch, and the cache latch transmits the data dumped by the data latch to a data I/O circuit. While the cache latch included in at least one of the plurality of first page buffers is performing a data transmit operation, the data latch included in at least one of the plurality of second page buffers performs a data dumping operation.

Non-volatile memory device and operation method of the same

A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.

Memory system including a plurality of controllers

To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.

Memory device including NAND strings and method of operating the same

A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Memory system controlling peak current generation for a plurality of memories by synchronizing internal clock of each memory with a processor clock at different times to avoid peak current generation period overlapping

A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.

Memory device, memory system, and method of controlling read voltage of the memory device

A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.

Flash memory management method

A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times

A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.

Method of operating memory device

A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array.

Apparatus and method of operating memory device

A method of operating a memory device includes applying an initial read voltage to a selected wordline to perform a read operation on memory cells connected to the selected wordline, determining whether a read failure occurs with respect to one or more of the memory cells, upon determining that a read failure has occurred with respect to some of the memory cells, determining threshold voltage distribution information for distinct groups of the memory cells, and determining a new read voltage to be applied to the selected wordline based on the threshold voltage distribution information.

Memory device and method of determining read voltage of memory device

Growing community of inventors

Yongin-si, South Korea

Jae-Yong Jeong