Skhynix Inc.

Jae Yeop Jung

Sung Hyun Hwang

Dong Hun Kwak

Hyung Jin Choi

Se Chun Park

Chan Hui Jeong

Jong Kyung Park

A memory device includes: memory cells connected between a common source line and bit lines; a source line driver for applying a common source line voltage to the common source line and then floating the common source line; and a program operation controller for controlling the source line driver to change a length of a floating period in which the common source line is floated, based on a degree to which a program operation on the memory cells is performed.

Memory device and operating method of the memory device for reducing power consumption for program operation

A memory device comprising: a memory cell array including memory cells coupled between a word line and a plurality of bit lines, and a control unit suitable for performing a program operation of repeating a program loop including a voltage application operation and a verification operation on the memory cells according to an Incremental Step Pulse Program (ISPP) method until the program operation is performed successfully, wherein the control unit repeatedly performs the program loop by setting a voltage level of an initial program pulse to one of first and second levels according to whether the program operation is an overwrite operation or not, wherein the initial program pulse is to be applied to the word line in the voltage application operation included in an initial program loop of the repeated program loops, and wherein the second level is lower than the first level by a first set level.

Memory device permitting overwrite program operation and operation method thereof

Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells coupled between a common source line and a bit line, a peripheral circuit configured to perform a plurality of program loops, each including a program voltage application operation of applying a program voltage to a selected memory cell and a verify operation of verifying a program state of the selected memory cell, and a control logic configured to control, at the program voltage application operation, the peripheral circuit to apply a precharge voltage to the common source line and change at least one of a magnitude of the precharge voltage and a time during which the precharge voltage is applied, depending on a magnitude of the program voltage.

Memory device for performing program operation and method of operating the same

Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cell strings, a peripheral circuit configured to, using a plurality of read voltages, perform a read operation that reads data that is stored in a selected memory cell that is included in a selected memory cell string, and an operation controller configured to control the peripheral circuit to perform the read operation by using a first read voltage, a first potential adjustment operation, and the read operation by using a second read voltage that is lower than the first read voltage, wherein the first potential adjustment operation is an operation that applies a first turn-on voltage to unselected source select lines that are coupled to unselected memory cell strings for a first period and thereafter applies a ground voltage to the unselected source select lines.

Memory device and method of operating the same

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on selected memory cells coupled to a selected word line among the plurality of memory cells. The control logic may control the program operation of the peripheral circuit. The program operation may include a plurality of program loops. Each of the program loops may include a program phase and a verify phase. The verify phase may include one or more verify operations. The control logic may be further configured to count a number of the verify operations performed by the peripheral circuit in the verify phase included in one of the plurality of program loops during the program operation.

Semiconductor memory device detecting program failure, and method of operating the same

A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.

Memory device and operating method of the memory device

A memory device having an improved operation speed may include a memory block including memory cells, a peripheral circuit configured to perform a program operation of increasing each of threshold voltages of the memory cells, and a control logic configured to control the peripheral circuit to perform the program operation. The program operation may include a plurality of program loops, each of the plurality of program loops may include a program voltage apply operation and a verify operation, and the control logic may control the peripheral circuit to perform verification on a highest program state during a verify operation included in a next program loop of any one program loop, when verification of a next higher program state among the plurality of program states is passed during a verify operation included in the any one program loop among the plurality of program loops.

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Gyeonggi-do, South Korea

Jae Yeop Jung