Nvidia Corporation

Jae Wu

Shantanu Sarangi

Rajith Mavila

Andi Skende

Mahmut Yilmaz

Anitha Kalva

Sailendra Chadalavada

Kaushik Narayanun

Milind Sonawane

Chen Fang

Abilash Nerallapally

Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.

Asynchronous in-system testing for autonomous systems and applications

Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

In system test of chips in functional systems

In-system test of chips in functional systems

The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

Controlling test networks of chips using integrated processors

Growing community of inventors

Santa Clara, CA, United States of America

Jae Wu