International Business Machines Corporation

Globalfoundries Inc.

Sumitomo Bakelite Company Limited

Disco Corporation

Ultratech, Inc.

Front Edge Technology, Inc.

Jae-Woong Nah

Peter Alfred Gruber

Paul Alfred Lauro

John Ulrich Knickerbocker

Bing Dang

Da-Yuan Shih

Eric Peter Lewandowski

Bucknell Chapman Webb

Stephen L Buchwalter

Michael A Gaynes

Katsuyuki Sakuma

Paul Stephen Andry

Adinath S Narasgond

Devendra K Sadana

Jeehwan Kim

Li-Wen Hung

Shriya Kumar

Russell Alan Budd

Claudius Feger

Robert J Polastre

Mark Harrison McLeod

Evan G Colgan

Yves Corfield Martin

Tymon Barwicz

Eric D Perfecto

Bruce Kenneth Furman

Qianwen Chen

Kang-Wook Lee

Peter Jerome Sorce

Keith E Fogel

Kuen-Ting Shiu

Frank Robert Libsch

Minhua Lu

Augustin J Hong

Hanhee Paik

Cornelia Kang-I Tsang

Charles L Reynolds

Robert E Trzcinski

Bo Wen

Jeng-Bang Yau

Jeffrey Donald Gelorme

Jerry M Chow

Peter Jeffrey Brofman

Nicholas Torleiv Bronn

Yang Liu

Kazushige Toriyama

Valerie A Oberson

Satoru Katsurayama

Leanna Pancoast

Nathalie Normand

Claudius Ferger

Mukta G Farooq

Kai Liu

Baleegh Abdo

Dongbing Shao

James L Speidell

Paul Francis Fortier

Martin O Sandberg

Jared Barney Hertzberg

Brian Michael Erwin

Yu Luo

Nicholas A Polomoff

Richard Francis Indyk

Rajneesh Kumar

Soojae Park

Robert P Kuder, Ii

Joana Sofia Branquinho Teresa Maria

Lavanya Turlapati

Shigefumi Okada

Pascal P Blais

Woo-Shik Jung

Daisuke Oka

Po-wen Cheng

Tung-hsiu Shih

Mengnian Niu

Kai-wei Nieh

Adinath Shantinath Narasgond

Victor Alvarez

Pierre Y Beaulieu

Sébastien S Quesnel

Robert L Toutant

Alain A Warren

A structure includes a first device having a first chip and a second chip. The second chip has a first side with a plurality of bumps and a second side with a plurality of first superconducting lines. A solder bonded layer attaches the first chip to the second chip. A second device has a first side with a plurality of pads facing the plurality of bumps in the second chip and a second side opposite the first side having a plurality of second superconducting lines. A solder shield material surrounds the plurality of bumps and the plurality of pads, and the plurality of bumps on the second chip are bonded to the plurality of pads on the second device. The solder shield material is connected to the plurality of first superconducting lines of the first device and to the plurality of second superconducting lines of the second device.

Solder-shielded chip bonding

Systems and techniques that facilitate uniform qubit chip gaps via injection-molded solder pillars are provided. In various embodiments, a device can comprise one or more injection-molded solder interconnects. In various aspects, the one or more injection-molded solder interconnects can couple at least one qubit chip to an interposer chip. In various embodiments, the device can further comprise one or more injection-molded solder pillars. In various instances, the one or more injection-molded solder pillars can be between the at least one quit chip and the interposer chip. In various cases, the one or more injection-molded solder pillars can be in parallel with the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can facilitate and/or maintain a uniform gap between the at least one qubit chip and the interposer chip. In various embodiments, a melting point of the one or more injection-molded solder pillars can be higher than a melting point of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be superconductors. In various embodiments, a yield strength of the one or more injection-molded solder pillars can be between 3,000 pounds per square inch and 15,000 pounds per square inch, which can be higher than a yield strength of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be binary tin alloys, tertiary tin alloys, and/or quaternary tin alloys.

Uniform chip gaps via injection-molded solder pillars

In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.

System and method for forming solder bumps

An improved molten solder injection head having a vacuum filter and differential gauge system is provided. In one aspect, an injection head is provided. The injection head includes: a reservoir; an injection port on a bottom of the injection head connected to the reservoir; a vacuum port adjacent to the injection port on the bottom of the injection head connected to a vacuum source; and a filter disposed between the bottom of the injection head and the vacuum source. A method for molten solder injection using the present injection head is provided.

Molten solder injection head with vacuum filter and differential gauge system

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

Hybrid under-bump metallization component

A method and apparatus for bonding a processor wafer with a microchannel wafer/glass manifold to form a bonded wafer structure are provided. A glass fixture is also provided for protecting C4 solder bumps on chips disposed on the processor wafer. When the glass fixture is positioned on the processor wafer, posts extending from the glass fixture contact corresponding regions on the processor wafer devoid of C4 solder bumps, so that the glass fixture protects the C4 solder bumps during wafer bonding. The method involves positioning the processor wafer/glass fixture and the microchannel wafer/glass manifold in a metal fixture having one or more alignment structures adapted to engage corresponding alignment elements formed in the processor wafer, glass fixture and/or glass manifold. The metal fixture secures the wafer components in place and, after melting solder pellets disposed between the processor wafer/glass fixture and microchannel wafer/glass manifold, a bonded wafer structure is formed.

Method and apparatus of processor wafer bonding for wafer-scale integrated supercomputer

Apparatus and methods are disclosed for transferring solder to a substrate. A substrate belt moves one or more substrates in a belt direction. A decal has one or more through holes in a hole pattern that hold solder. Each of the solder holes can align with respective locations on one of the substrates. An ultrasonic head produces an ultrasonic vibration in the solder in a longitudinal direction perpendicular to the belt direction. The ultrasonic head and substrate can be moved together in the longitudinal direction to maintain the ultrasonic head in contact with the solder while the ultrasonic head applies the ultrasonic vibration. Various methods are disclosed including methods of transferring the solder with or without external heating.

Ultrasonic-assisted solder transfer

Microbatteries and methods for forming microbatteries are provided. The microbatteries and methods address at least one or both of edge sealing issues for edges of a stack forming part of a microbatteries and overall sealing for individual cells for microbatteries in a batch process. A transferable solder molding apparatus and sealing structure are proposed in an example to provide a metal casing for a solid-state thin-film microbattery. An exemplary proposed process involves deposition or pre-forming low-temperature solder casing separately from the microbatteries. Then a thermal compression may be used to transfer the solder casing to each battery cell, with a handler apparatus in a batch process in an example. These exemplary embodiments can address the temperature tolerance constrain for solid state thin film battery during handling, metal sealing, and packaging.

Ultra-thin microbattery packaging and handling

A method of manufacturing a micro-battery is provided. The method includes forming a micro-battery device by forming a first metal anode via and a first metal cathode via in a first substrate, forming a first metal layer on a bottom side of the first substrate, forming a first battery element on a top side of the substrate, forming an encapsulation layer around the first battery element, forming trenches through the encapsulation layer and the first substrate on different sides of the first battery element, and forming a metal sealing layer in the trenches to cover at least a plurality of sidewall surfaces of the first battery element. The metal sealing layer is electrically connected to the battery element through the first metal layer and the first metal cathode via.

Hermetic packaging of a micro-battery device

A micro-battery is provided in which a metallic sealing layer is used to provide a hermetic seal between an anode side of the micro-battery and the cathode side of the micro-battery. In accordance with the present application, the metallic sealing layer is formed around a perimeter of each metallic anode structure located on the anode side and then the metallic sealing layer is bonded to a solderable metal layer of a wall structure present on the cathode side. The wall structure contains a cavity that exposes a metallic current collector structure, the cavity is filled with battery materials.

Simplified hermetic packaging of a micro-battery

A modular superconducting quantum processor includes a first superconducting chip including a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency, and a second superconducting chip including a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency. The quantum processor further includes an interposer chip connected to the first superconducting chip and to the second superconducting chip. The interposer chip has interposer coupler elements configured to couple the second plurality of qubits to the fourth plurality of qubits.

Modular, frequency-flexible, superconducting quantum processor architecture

Protruding solder structures are created for electrical attachment of semiconductor devices. A rigid mold having one or more mold openings is attached to and used in combination with a decal structure that has one or more decal holes. The decal structure is disposed on the rigid mold so that the decal openings are aligned over the mold openings. Each of the decal hole and mold opening in contact form a single combined volume. The single combined volumes are filled with solder to form protruding solder structures. Various structures and methods of making and using the structures are disclosed.

Combination polyimide decal with a rigid mold

Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 &#x3bc;m to about 100 &#x3bc;m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.

High speed handling of ultra-small chips by selective laser bonding and debonding

A method of manufacturing a multi-layer wafer is provided. Under bump metallization (UMB) pads are created on each of two heterogeneous wafers. A conductive means is applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The stress compensating polymer layer has a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition.

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

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Closter, NJ, United States of America

Jae-Woong Nah