Dorco Co., Ltd.

Samsung Electronics Co., Ltd.

Jae Woong Lee

Hyun Tae Kim

Hee Jong Shin

Sung Woo Lee

Eui-Hwan Cho

Sang-Hyuk Kwon

Hyosun Ahn

Byung Hoon Jeong

Seung Mi Shin

Seungmi Shin

Su Hyun Chae

Myeong O Kim

Jong Bae Yoon

Ki Seok Park

Ho Tae Nam

Sung Ju Choi

Ankit Bhandari

Jong Hyuk Jang

Woo-Heon Song

Ho Joon Park

Jeong Ho Joo

Ho Seok Kwon

Razor handle

Razor cartridge

An electronic device is provided. The electronic device includes a memory configured to store contents, a display configured to output the contents, and a processor operatively connected with the memory and the display. The memory is further configured to store instructions that, when executed, cause the processor to, in response to a first user input, select at least one contents satisfying a specified condition among a plurality of contents stored in the memory, output a first screen composed of the selected at least one contents in the display, and if a second user input to end the output of the first screen is received, output a second screen for verification of a user of the electronic device in the display.

Contents securing method and electronic device supporting the same

In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.

Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same

A semiconductor memory device and a parallel bit test method thereof comprises a memory cell array having a plurality of memory cells, an address generator for accessing memory cells of the memory cell array in response to externally applied addresses; a test mode setting register for storing an externally applied test mode setting command; a test pattern data register for storing test pattern data applied from the test mode setting register and for outputting test pattern data at the time of performing a read command; and a comparator for comparing data read from the memory cells of the memory cell array with data of corresponding bits of test pattern data output from the test pattern data register and for generating test result data. Accordingly, the device is adapted for correctly detecting and distinguishing defective memory cells, and is amenable to performing bit tests using various non-uniform test pattern data.

Semiconductor memory device and parallel bit test method thereof

Growing community of inventors

Seoul, South Korea

Jae Woong Lee