Samsung Electronics Co., Ltd.

Kia Motors Corporation

Jae-Woong Lee

Seong-Taek Hwang

Dong-Hyuk Lee

Do-Hyeon Kim

Dong-Chang Lee

Won-Suk Chang

Ji-Hoon Kim

Kang-jin Yoon

Hyong-Ryol Hwang

Gun-Ill Lee

Jei-hwan Yoo

Kyung-su Kim

Ho-Young Jung

Jong-hak Won

Wol-Jin Lee

Byung-joon Chang

Byung-Kyu Ho

Won-jun Roh

Chan-Min Park

In-Sang Cho

A method for creating handwriting content is provided. The method includes displaying handwriting letters being input, extracting at least one candidate handwriting word stored in advance in response to the input handwriting letters, displaying the extracted at least one candidate handwriting word, and replacing the input handwriting letters with a candidate handwriting word selected from among the displayed at least one candidate handwriting word.

User device and method for creating handwriting content

A method of providing a Graphical User Interface (GUI) is provided. The method includes receiving an image to be used for the GUI, and selecting one or more object areas to be used for the GUI from the image, setting a GUI icon corresponding to the selected object area, and outputting the set GUI as a home screen for executing at least one of application on a display of the terminal.

Method and apparatus for providing graphic user interface

A method of performing multiple data bus inversion (DBI) and a memory device performing the method are provided. The multiple DBI includes first through third DBI operations, wherein the first DBI operation determines whether to perform data inversion on a first data inversion group in which M&#xd7;N data bits of a M&#xd7;N data bit structure are grouped and performs the data inversion on the first data inversion group, the second DBI operation determines whether to perform data inversion on second data inversion groups formed by grouping M data bits from among the M&#xd7;N data bits and performs the data inversion on the second data inversion groups, and the third DBI operation determines whether to perform data inversion on third data inversion groups formed by grouping N data bits from among the M&#xd7;N data bits and performs the data inversion on the third data inversion groups.

Methods of performing multiple data bus inversion (DBI) and memory devices performing the methods

A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written.

Volatile memory device and memory controller

A column decoder of a semiconductor memory device includes an internal address output circuit, an address decoder, and a control circuit. The internal address output circuit converts an external column address into an internal column address and outputs the internal column address. The address decoder decodes a pre-decoded column address, which is obtained by decoding the internal column address, in response to a write column enable signal or in response to a read column enable signal activated earlier than the write column enable signal, and generates a column selection line signal for activating a memory cell designated by the external column address. The control circuit outputs a write signal or a read signal for controlling an output time of the internal column address. The address decoder generates a valid column selection line signal in response to a write signal in the write operation, and generates a valid column selection line signal in response to the read signal in a read operation.

Column decoder of semiconductor memory device, and method of generating column selection line signal in semiconductor memory device

A semiconductor memory device having a hierarchical I/O line structure is provided. The semiconductor memory array includes a memory cell array which is divided into a plurality of sub-arrays by sub-word line driver areas and bit line sense amplifier areas; local input/output (I/O) lines which are arranged in the bit line sense amplifier areas; and global I/O lines which are arranged in the sub-word line driver areas, wherein at least one end of each of the local I/O lines is formed in a bit line sense amplifier area. The semiconductor memory device may also have a dummy bit line sense amplifier area capable of dividing local I/O lines in a bit line sense amplifier area, and can reduce the number of sub-word line driver areas such that the chip size can be reduced.

Scalable hierarchical I/O line structure for a semiconductor memory device

A semiconductor memory device having an asynchronous data path is provided. The data path may compensate for differences between the path from a control circuit to memory banks and from memory banks to output pads of the semiconductor memory. The memory device may include first and second memory banks for storing data, output pads arranged adjacent to the second memory bank, and a control circuit arranged adjacent to the first memory bank for controlling operation of the first memory bank and the second memory bank in response to an external control signal. A first output circuit is adjacent the first memory bank for transmitting data from the first memory bank to the output pads in response to an output signal. A second output circuit is adjacent the second memory bank for transmitting data from the second memory bank to the output pads in response to the output signal.

Semiconductor memory device having asymmetric data paths

A semiconductor memory device comprising an architecture for minimizing the lengths of the I/O (input/output) data paths and the difference in length between the data paths. In one aspect, a semiconductor memory device comprises first and second pad groups, first, second, third and fourth banks and first and second circuits. The first pad group comprises a portion of the total number of pads and is located in proximity to the center of the chip, and the second pad group comprises the remaining pads. The first, second, third and fourth banks include first and second, third and fourth, fifth and sixth and seventh and eighth blocks having memory cells, respectively, and further include first and second, third and fourth, fifth and sixth and seventh and eighth I/O units for inputting and outputting the data in the first through fourth blocks, respectively. The first circuit is connected between the first pad group and the odd-numbered I/O units of the banks, and performs multiplexing. The second circuit is connected between the second pad group and the even-numbered I/O units of the banks, and performs multiplexing. The banks and circuits are disposed on the semiconductor device such that the data buses connecting the corresponding banks and circuits are substantially the same length and width. Each of the first and second circuits can be replaced with a plurality of I/O sense amplifiers, and the I/O units can be replaced with I/O multiplexers.

Semiconductor memory architecture for minimizing input/output data paths

A circuit and method are shown for controlling a redundant memory cell of an integrated memory circuit. The circuit includes a decoder, a precharge enable unit, a redundant controller, a redundant enable signal generator, and a redundant memory cell array. The precharge enable unit is connected to the decoder, and responds to a precharge enable signal by precharging the output terminal of decoder. The decoder responds to a first row address signal by discharging the output terminal of the decoder unless the value of the row address signal corresponds to a programmed address of the decoder. The redundant enable signal generator samples the voltage level of the output terminal of the decoder under control of a redundant control signal of the redundant controller in order to generate a redundant cell enable signal. The redundant controller generates the redundant control signal in response to a second row address signal, where the redundant controller delays the redundant control signal by a predetermined time interval in response to a stress test signal which is active during a stress test in order to allow the decoder sufficient time to discharge the output terminal during the stress test. The redundant memory cell array is connected to the redundant enable signal generator and responds to the redundant enable signal.

Circuit and method for controlling a redundant memory cell in an

Disclosed is a magnetic brake system for a vehicle, comprising: a plurality of brake disk solenoids for generating the magnetic force; a plurality of brake pad solenoids for generating the magnetic force; a braking sensor for detecting whether a brake pedal is applied; a wheel speed sensor for detecting wheel speed; a magnetic polarity sensor for detecting magnetic polarity of the brake disk solenoids; and a control unit for controlling the brake pad solenoids using signals from the braking sensor, the wheel speed sensor and the magnetic polarity sensor.

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Seoul, South Korea

Jae-Woong Lee