Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Jae-Woo Seo

Ha-Young Kim

Dal-Hee Lee

Jin Tae Kim

Youngsoo Shin

Jin-Tae Kim

Dong-yeon Heo

Sang-Hoon Baek

Jisu Yu

Gi-young Yang

Jinwook Jung

Sungwe Cho

Keunho Lee

Hyeongyu You

Yong-Ho Hwang

Tae Joong Song

Keun Ho Lee

Hyoung-Suk Oh

Sung-Wee Cho

Dal Hee Lee

Min-Ho Park

Junghwan Shin

Hyun-Jeong Roh

Ki-Man Park

Sung We Cho

Min-Su Kim

Hyuk Kang

Minjae Jeong

Sanghoon Baek

Myung-Sun Kim

Yong-ho Kim

Uk-Rae Cho

Jae-Bong Chun

Jungho Do

Gyu-Cheol Choi

Gun-Ok Jung

Sung-Hyuk Shin

Woo-chul Shim

Hyeon Gyu You

Yu-na Kim

Jaeha Lee

Ga-Jin Song

Sung-We Cho

Ji Su Yu

Sung-Hyun Park

Myung-Gon Hong

Ho-jung Lee

Ju-Hyun Kang

Yu-Na Kim

Woo-Jin Rim

Jung-Hee Cheon

Jae-Ha Lee

Choong-hoon Lee

Seung Man Lim

Mi-Ran Kim

Sang-shin Han

JinTae Kim

A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.

Cooling device semiconductor device including end curved interconnection lines

Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

Semiconductor device

An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.

Integrated circuit including standard cells

A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.

Semiconductor device including a gate pitch and an interconnection line pitch and a method for manufacturing the same

Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same

An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

Standard cell for removing routing interference between adjacent pins and device including the same

A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

Integrated circuit and method of designing layout of integrated circuit

An electronic device is provided. The electronic device includes a memory configured to store information associated with a user, and a query managing module that is functionally connected with the memory wherein the query managing module is configured to execute acquiring a query, determining at least one word associated with the user, from the query, obtaining a result of a first search executed, based on the at least one word, from a set of protected data associated with the user, changing at least a part of the query, based on the result of the first search, and providing a result of a second search executed, based on the changed query, from a set of public data.

Apparatus and method for processing query

Growing community of inventors

Seoul, South Korea

Jae-Woo Seo