Samsung Electronics Co., Ltd.

Jae Woo Park

Jung Hwan Choi

Young Chul Cho

Young Don Choi

Myoung Bo Kwak

Seung Jin Park

Hyeok Jun Choi

Kyoung Jun Roh

Seung Kap Lee

Chun Mo Sung

Young Min Ku

Jun Han Choi

Jin Ook Jung

A data receiving device may include a dummy stage block. The dummy stage block may include m dummy stages, wherein m is a natural number greater than or equal to two. Each of the m dummy stages may be configured to remove inter-symbol interference (ISI) from a dummy input signal using dummy coefficient information to generate a dummy output signal free of the ISI. Each of the m dummy stages may be further configured to output the dummy output signal. A normal stage block may include n normal stages, wherein n is a natural number greater than or equal to two. Each of the n normal stages may be configured to remove ISI from an input signal using coefficient information to generate an output signal free of the ISI and may be further configured to output the output signal.

Data receiving device

A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.

Semiconductor device and memory device comprising the same

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Memory device, operating method of the memory device and memory system comprising the memory device

A variable capacity rotary compressor to securely fix a clutch pin to a rotation shaft includes first and second compression chambers having different inner volumes, a rotation shaft penetrating the first and second compression chambers, first and second eccentric bushes disposed on an outer circumference of the rotation shaft, a slot provided between the first and second eccentric bushes, a clutch pin protruding from the rotation shaft and disposed in the slot, and a fixing pin coupled with the side of the clutch pin in the rotation shaft to securely fix the clutch pin to the rotation shaft. A groove having a predetermined width can be formed at a rear side of the clutch pin and a rear side of the fixing pin can be inserted into the groove to couple with the clutch pin in the rotation shaft.

Variable capacity rotary compressor

Growing community of inventors

Suwon-si, South Korea

Jae Woo Park