Samsung Electronics Co., Ltd.

Skhynix Inc.

Jae-Woo Kim

Tae-Pyeong Kim

Hyun-Jin Noh

Pyo-Young Han

Yong-Sun Ko

Sang-sup Jeong

Sung-Nam Chang

Kwang-Shik Shin

Hee-Beom Kang

Myeong-Gu Lee

A method for operating a memory system includes: performing a first training operation for alignment between a clock and a data strobe signal; performing a second training operation for alignment between the data strobe signal and the data; detecting an error of the second training operation; and adjusting a delay value of the data strobe signal in response to the detection of the error.

Memory system, operation method of the same, and memory controller

A method of fabricating a semiconductor device including sequentially forming a polysilicon layer, a first insulating layer, and a photoresist layer over a gate oxide film positioned on a semiconductor substrate. A photoresist pattern with a first groove is formed by selectively patterning the photoresist layer to partially expose a surface of the first insulating layer. A second insulating layer is formed over the photoresist pattern with the first groove and over the exposed surface of the first insulating layer. A sacrificial spacer is formed on each inner wall of the first groove by etching back the second insulating layer and forming a second groove in the first insulating layer in communication with the first groove to expose a surface of the polysilicon layer at the bottom of the second groove. The photoresist pattern is removed, and an arbitrary layer pattern is formed over the polysilicon layer at the bottom of the second groove. The sacrificial spacers and first insulating layer are removed, and a gate electrode is formed by etching the polysilicon layer using the arbitrary layer pattern as a mask.

Method of fabricating a semiconductor device

A method for fabricating a floating gate in a non-volatile memory device and a floating gate fabricated using the same are provided. A conductive layer having upper and lower portions is formed over a substrate with field regions formed therein. A hard mask layer is formed over the conductive layer. Next, a photoresist pattern is formed over the hard mask layer. The hard mask layer is etched to form a hard mask pattern, using the photoresist pattern as an etching mask. The upper portion of the conductive layer is slope-etched, leaving the lower portion of the conductive layer intact, using the photoresist pattern as an etching mask. The slope-etched upper portion of the conductive layer is again vertically etched and the lower portion of the conductive layer is concurrently slope-etched, using the hard pattern as an etching mask. With the present invention, a bridge between floating gates can be reduced, and field loss can be reduced during processing steps such as an ONO etching process.

Method for fabricating floating gate

Growing community of inventors

Gyeonggi-do, South Korea

Jae-Woo Kim