Lg Electronics Inc.

Ulsan National Institute of Science and Technology

Samsung Display Co., Ltd.

Sungkyunkwan University

Korea Institute of Industrial Technology

Unist (ulsan National Institute of Science and Technology )

Infinitt Healthcare Co., Ltd.

Sk Chemicals Co., Ltd.

Jae Won Jeong

Kyung Rok Kim

Seon Kyu Kim

Sang Yoon Lee

Tae Hyun Sung

Tae Il Kim

Kyu Nam Lee

Jung Joo Yoo

In Hyeuk Choi

Kang Eui Cho

Jae Hung Chun

Wooseok Kim

Youngeun Choi

Young Eun Choi

Ji Eun Kim

Ji Won Chang

Woo Seok Kim

Sang Hyun Lee

Jin Ku Cho

Sang Yong Kim

June Kyun Park

Yong Han Roh

Byung Chan Seo

Do Hoon Lee

Po-Yun Park

Kwan-Young Oh

Kyung-Uk Choi

Bo Ra Kim

Baek Jin Kim

Seung Han Shin

Kyung Uk Choi

Ji Woong Jeong

Sangyoung Lee

E San Jang

Younjin Jung

Jae Hyeon Jun

Jiwon Chang

Sun Hae Shin

A transistor device includes a substrate, a source region provided on the substrate, a drain region in the substrate, spaced apart from the source region in a direction parallel to a top surface of the substrate, a gate electrode provided on the substrate and between the source region and the drain region, a gate insulating film interposed between the gate electrode and the substrate, and a constant current generating layer extending between the source region and the drain region, in the direction parallel to the top surface of the substrate, wherein the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Transistor device, ternary inverter device including same, and manufacturing method therefor

A transistor device includes a substrate, a source region provided on the substrate, a drain region spaced apart from the source region in a direction parallel to a top surface of the substrate, a pair of constant current generating patterns provided in the substrate to be adjacent to the source region and the drain region, respectively, a gate electrode provided on the substrate and between the source region and the drain region, and a gate insulating film interposed between the gate electrode and the substrate, wherein, the pair of constant current generating patterns generate a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Transistor element, ternary inverter apparatus comprising same, and method for producing same

Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

Ternary inverter and method of manufacturing the same

In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

Ternary memory cell and memory device comprising same

Provided is a transistor including: a constant current formation layer; a channel layer provided on the constant current formation layer; a pair of source/drain regions spaced apart from each other, with the channel layer therebetween on the constant current formation layer; a gate electrode provided on the channel layer; and a gate ferroelectric film provided between the gate electrode and the channel layer.

Transistor, ternary inverter comprising same, and transistor manufacturing method

A transistor includes a substrate; a pair of constant current forming regions provided in the substrate; a pair of source/drain regions respectively provided on the pair of constant current forming regions in the substrate; and a gate structure provided between the pair of source/drain regions, wherein any one of the constant current forming regions immediately adjacent to any one of the pair of source/drain regions serving as a drain forms a constant current between the any one of the pair of source/drain region serving as the drain and the any one of the constant current forming regions.

Transistor, ternary inverter including same, and transistor manufacturing method

A tunnel field effect transistor includes a constant current formation layer, a source region and a drain region provided on the constant current formation layer, a channel layer provided between the source region and the drain region, a gate electrode provided on the channel layer, and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region have different conductivity types, and the constant current formation layer forms a constant current between the drain region and the constant current formation layer.

Tunnel field effect transistor and ternary inverter comprising same

A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

Ternary logic circuit

A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

According to an embodiment of the present disclosure, a memory device for a logic-in-memory may include a cell array including a plurality of ternary memory cells, a row decoder configured to select at least one ternary memory cell from among the plurality of ternary memory cells, and a page buffer configured to provide a first value to the at least one ternary memory cell and latch a third value obtained by performing a logic operation on the first value and a second value stored in the at least one ternary memory cell and/or the second value. The at least one ternary memory cell may include: a first inverter and a second inverter, cross-coupled in a first node corresponding to the second value and a second node corresponding to an inverted value of the second value, and including a pull-up device and a pull-down device, wherein the pull-up device and the pull-down device are configured to have a constant current pass therethrough upon turn-off; and a logic operation circuit including a P-channel transistor and an N-channel transistor and configured to output the third value, wherein the P-channel transistor and the N-channel transistor are configured to have the constant current pass therethrough upon turn-off.

Ternary memory cell for logic-in-memory and memory device comprising same

The present disclosure relates to an organic light emitting device including: a first electrode; a second electrode provided to face the first electrode; and an electron transport layer, an emitting layer and a hole transport layer provided between the first electrode and the second electrode, and the emitting layer contains doped protein quantum dots.

Organic light emitting device

A ternary logic circuit according to the present invention includes a pull-up device () and a pull-down device () connected in series between power voltage sources (Vand GND), and an input voltage (V) source and output voltage (V) source. When both the pull-up device () and the pull-down device () are turned off by an input voltage (V), both the pull-up device () and the pull-down device () operate as simple resistors which are affected only by an output voltage (V) and form a ternary digit ('1' state) through voltage division. When only one of the pull-up device () or the pull-down device () is turned on to allow a current to flow therethrough, V('2' state) or GND (&#x201c;0&#x201d; state) is output as the output voltage (V). Accordingly, a bit density can be remarkably increased.

Ternary digit logic circuit

Provided herein is a control method of a touch screen panel having an activated area divided into a plurality of touch areas, and a plurality of touch drivers each corresponding to each of the touch areas, the method including computing location information of a stylus pen based on photograph data; and controlling power of the touch drivers according to the computed location information.

Touch screen panel and control method thereof

A liquid crystal display device includes a liquid crystal panel which includes gate lines, data lines crossing the gate lines, and pixels connected to the gate lines and the data lines; a timing controller for receiving a control signal and image data and for generating a gate control signal and a data control signal; a gate driver for generating a gate signal based on the gate control signal and outputting the gate signal to the gate lines; and a data driver for performing data conversion on the image data based on the data control signal and outputting a conversion result to the data lines, wherein the timing controller analyzes the image data frame by frame data and applies two or more inversion driving techniques to frame data.

Liquid crystal display apparatus using inversion driving and driving method thereof

Growing community of inventors

Seoul, South Korea

Jae Won Jeong