Samsung Electronics Co., Ltd.

Jae-Won Hwang

Byung-Hee Kim

Jong-Jin Lee

Rak-Hwan Kim

Nae-in Lee

Jin-Nam Kim

Eun-Ji Jung

Jae-Won Chang

Tsukasa Matsuda

Ho-Yun Jeon

Kyoung-Hee Nam

Wan-Soo Park

Jeong-Ok Cha

Jung-Ha Hwang

Dea-Yun Kim

Eun-Ju Kang

A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.

Semiconductor device with a conductive liner

In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

Methods of forming wiring structures including a plurality of metal layers

A polishing system controls the durations over which different layers on a substrate are sequentially polished. The polishing system polishes an upper layer using an endpoint detection technique and polishes a lower layer using a closed loop control technique. Once the lower layer is detected during the course of polishing the upper layer, the polishing system automatically enters the recipe for polishing the lower layer under a closed loop control mode.

Method of and apparatus for controlling the chemical mechanical polishing of multiple layers on a substrate

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Seongnam-si, South Korea

Jae-Won Hwang