Dongbu Electronics, Co. Ltd.

Dongbu Hitek Co., Ltd.

Anam Semiconductor Inc.

Other

Dongbu Anam Semiconductor, Inc.

Jae Won Han

Sang Chul Kim

Kyung Min Park

Hyun Soo Shin

A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Aluminum metal line of a semiconductor device and method of fabricating the same

Disclosed are an image sensor and a method for manufacturing the same, capable of increasing a light absorbing coefficient by forming a rough surface on a photodiode. The image sensor includes a semiconductor substrate with a plurality of photodiodes thereon having rough upper surfaces, a dielectric layer on the semiconductor substrate, a color filter layer on the dielectric layer, a planarization layer on an entire surface of the semiconductor substrate including the color filter layer, and a plurality of micro-lenses formed on the planarization layer to correspond to the color filter layer.

Image sensor and method for manufacturing the same

A semiconductor device and fabricating method thereof are provided. A first substrate with an inductor cell and a through-electrode is connected to a second substrate having an RF device circuit unit. The first substrate can be stacked on the second substrate, and a connecting electrode can electrically connect the inductor cell to the RF device circuit unit.

Fabricating method of a semiconductor device

An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the circuit part of the second wafer.

Disclosed is a method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor. The present method includes a low-voltage well implantation process on a semiconductor substrate to form a first well in a first region of the substrate and a second well in a second region of the substrate; forming first and second gate oxide layers and first and second gate electrodes in the first and second regions, respectively; forming a first photoresist pattern to expose the first region; forming a first LDD region in the first region exposed by the first photoresist pattern and the first gate electrode; removing the first photoresist pattern; forming a second photoresist pattern to expose the second region; forming a second LDD region in the second region exposed by the second photoresist pattern and the second gate electrode; performing a compensational implantation on the second region to adjust a well concentration for the high-voltage MOS transistor; and removing the second photoresist pattern.

Method for manufacturing MOS transistor of semiconductor device

A semiconductor device and a fabricating method thereof are provided. A PMD layer and at least one IMD layer are formed on a semiconductor substrate. A through-electrode penetrates through the PMD layer and the IMD layer, and a connecting electrode connects to the through-electrode.

Semiconductor device and fabricating method thereof

An image sensor according to embodiments may include a first substrate having photodiode cells, a second substrate having a logic circuit, and connection electrodes that may electrically connect the photodiode cells with the logic circuit. In embodiments, more area may be available on the first substrate for photodiode cells and light loss may be reduced.

Image sensor

A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.

Method for manufacturing semiconductor device

A sputtering apparatus for forming a low-resistance uniform metal silicide layer without additional heat treatment and a metal silicide layer forming method using the same are provided. The sputtering apparatus includes a sputtering chamber; a gas introduction port formed at an upper location of a lateral wall of the sputtering chamber; a gas exhaust port formed at a bottom wall of the sputtering chamber; a target located in an upper region of the sputtering chamber; a power source to supply the target with high-frequency electric power; a stage located in a bottom region of the sputtering chamber to heat the semiconductor substrate; and a sieve provided between the target and the semiconductor substrate to improve straightness of charged metal particles.

Sputtering apparatus and method for forming metal silicide layer using the same

A metal wiring for a semiconductor device and a method for forming the same are provided. The metal wiring includes a first insulating layer and a second insulating layer; an interlayer insulating film formed between the first and second insulating layers, wherein the interlayer insulating film is provided with holes having a designated shape; a barrier metal layer, a copper seed layer, and a copper layer sequentially formed in the holes of the interlayer insulating film; and a capping layer formed between the interlayer insulating film and the second insulating layer. The capping layer formed between the interlayer insulating film and the second insulating layer may be made of a negatively charged insulating material, thereby improving electro-migration characteristics at an interface between the capping layer and the copper layers.

Metal wiring for semiconductor device and method for forming the same

A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impurity ions into the first and second areas, respectively, and measuring a resistance of the standard pattern. The method also includes forming a misalignment inspection pattern consisting of a first area and a second area on a predetermined area within a semiconductor substrate, implanting first and second conduction type impurity ions into the misalignment inspection pattern and active regions on the semiconductor substrate, respectively, and measuring a resistance of the misalignment inspection pattern. The method concludes by comparing the resistance of the standard pattern with the resistance of the misalignment inspection pattern.

Method of detecting misalignment of ion implantation area

A method of forming a barrier metal in a semiconductor device. The present invention includes forming an insulating layer on a substrate having a lower metal line formed thereon, forming an opening exposing the lower metal line through the insulating layer, and forming a barrier metal layer on a sidewall of the opening and the insulating layer except the lower metal line by applying a positive voltage to the substrate.

Method of forming barrier metal in semiconductor device

A method of fabricating a metal interconnection of semiconductor device is disclosed. A metal interconnection fabricating method according to the present invention comprises the steps of depositing a metal layer on a substrate having a predetermined structure; patterning a bottom metal layer through etching the metal layer; forming a pad electrically connecting the bottom metal layer to a scribe area; forming an insulating layer on the substrate including the bottom metal layer; forming a via hole and a trench, in which an upper metal layer is formed, on the insulating layer, the via hole connecting the bottom metal layer with the upper metal layer; forming a plating layer by means of electroplating; and performing a planarization process for the plating layer. Accordingly, the present invention needs not a separate seed layer because the bottom metal layer is used as a seed layer. In addition, the present invention can enhance device reliability by reducing electro-migration and stress-migration because the copper is uniformly grown from the bottom in one direction thereby completely filling the contact hole.

Growing community of inventors

Suwon-si, South Korea

Jae Won Han