Hyundai Electronics Industries Co. Ltd.

Other

Sam Yang Co., Ltd.

Jae Whan Kim

Beom Soo Kim

Young H Kim

Chang Zhu Jin

Dong Guk Paeng

Woog Y Lee

Jeong W An

Ja Moon Choi

Seung Hyun Yi

Proposed is a space monitoring apparatus using a sound signal and a space monitoring method thereof and, more specifically, is a technology in which a space monitoring apparatus using a sound to determine a spatial condition sets a synthesized sound having a plurality of frequency components to utilize the performance of a speaker efficiently and emits the synthesized sound to monitor the spatial condition.

Space monitoring apparatus using sound signal and space monitoring method thereof

A method of automatically setting an acoustic signal of a device for space monitoring by using the acoustic signal is proposed. The proposed is a technology for automatically setting the acoustic signal emitted from the device for space monitoring by using the acoustic signal for more precise measurement.

Method for automatic setting of sound signal in an apparatus for space monitoring by using sound signal

Proposed is a noise avoiding method for a space monitoring apparatus using a sound signal and, more specifically, is a technology that allows the space monitoring apparatus, which uses a sound signal to monitor a spatial condition, to avoid noise in a space to be monitored to correctly determine the spatial condition.

Method for avoiding noise in an apparatus for space monitoring by using sound signal

The present disclosure relates to an apparatus and method for monitoring a space using a three-dimensional acoustic web, and to a method of emitting a plurality of acoustic signals, forming a three-dimensional acoustic web in a monitoring target space based on interference between acoustic waves, and recognizing a situation of the monitoring target space based on a change in measured acoustic signals.

Apparatus for monitoring a space by using acoustic web

The present invention provides an improved ferroelectric capacitor used in a memory device by providing reliable electric interconnection between a lower electrode of the capacitor and an active region of transistor, and to provide a method for fabricating the same. A semiconductor capacitor according to the present invention comprises: a first conducting film filling an opening which is formed in an interlayer insulating film, being in contact with an active region of a semiconductor; a stacked charge storage node including a second conducting film formed on the first conducting film and an interlaying insulating film, a first diffusion preventing film formed on the second conducting film, a lower electrode film formed on the first diffusion preventing film, and a ferroelectric film formed on the lower electrode film; and a conducting spacer film formed on sidewalls of the lower electrode film, the first diffusion preventing film and the second conducting film.

Ferroelectric memory device guaranteeing electrical interconnection between lower capacitor electrode and contact plug and method for fabricating the same

A method of manufacturing a CMOS device which can prevent latch-up and easily apply to high integration device by completely isolating a N well and a P well in the back side of a substrate, is disclosed. A method of manufacturing a CMOS device according to the present invention, includes the steps of: providing a semiconductor having a back side and a front side, and including a N well and a P well formed therein respectively, a NMOS transistor formed on the P well, a PMOS transistor formed on the N well; etching the back side of the substrate along the PN junction portions of the N well and the P well to the front side of the substrate, thereby forming trenches; and, forming an insulating layer on the back side of the substrate to fill the trenches, thereby isolating the P well and the N well. Furthermore, a method of manufacturing a CMOS device according to the present invention, further includes the steps of: etching the insulating layer to expose portions of the P well and N well, thereby forming contact holes; forming a metal layer on the insulating layer to fill the contact holes; and patterning the metal layer to form an interconnection line.

Method of manufacturing CMOS device

A ferroelectric memory device includes memory cells consisted of a switching transistor and a ferroelectric capacitor for storing electric charges, word lines for enabling the switching transistor, positive and negative bit lines for transferring the electric charges, a sense amplifier for sensing a voltage difference between the positive and the negative bit lines and for amplifying the voltage levels of the positive and the negative bit lines. Positively pumped voltage is applied to the positive bit line while positive voltage lower than the positively pumped supply voltage is applied to the negative bit line. With the higher positive bit line, a sensing margin of the sense amplifier is improved and no separate reference cell is required for the sensing the voltage difference. Method for operating for the ferroelectric memory device is also disclosed.

Ferroelectric memory device and method for operating thereof

A ferroelectric memory device includes a plurality of groups of active areas, each active area having two memory cells, and a plurality of pairs of conductive lines arranged in a parallel fashion, each conductive line having a word line and a plate line, wherein a pair of the word line and the plate line are isolated through an insulating layer, wherein each group of the active areas are coupled to each pair of the conductive lines, thereby having a folded bit line architecture without increasing a chip size.

Ferroelectric memory device having folded bit line architecture

The present invention relates to semiconductor memory device and more particularly, to a technique for stabilizing the potential of the cell plate line by using two kinds of potentials for the cell plate line driver to implement the powerful driving force and rapid operability required in case of designing the RAM using as the memory device the material having large electrostatic capacity, and for preventing the loss of I/O by using CMOS transistors in the decoder circuit which receives the cell plate line voltage by cooperating with the cell plate line driver circuit and feeds back the cell plate line voltage.

Semiconductor memory device

The present invention relates a ferroelectric memory device capable of increasing the life time of the ferroelectric memory devices, by removing a reference ferroelectric capacitors with a smaller chip size. According to the present invention, the ferroelectric memory device uses a power supply Vcc as an reference voltage and doesn't have a reference cell consisting of ferroelectric capacitors. A plate voltage generator according to the present invention provides a plurality of voltage levels to a plate electrode of the ferroelectric capacitor at a read operation in order to use a power supply Vcc as a reference voltage of the sense amplifier, in response to first and second control signals, wherein the plate voltage generating means provides to the plate electrode a first voltage level Vcc+.alpha. more than a power supply Vcc by an additional voltage level .alpha. and a second voltage level of the power supply Vcc, in this order, wherein the first voltage level is provided to the plate electrode before the sense amplifier is enabled, wherein the second voltage level is provided to the plate electrode after the sense amplifier is enabled to restor the cell data in the ferroelectric capacitor, and wherein the additional voltage level is selected in a range that the bit line voltage corresponding to the logic data '0' is less than the reference voltage Vcc at the read operation.

Ferroelectric memory device increasing voltage on a bit line to remove

The present invention provides an improved ferroelectric capacitor used in a memory device by providing reliable electrical interconnection between a lower electrode of the capacitor and an active region of transistor, and to provide a method for fabricating the same. A semiconductor capacitor according to the present invention comprises: a first conducting film filling an opening which is formed in an interlayer insulating film, being in contact with an active region of a semiconductor; a stacked charge storage node including a second conducting film formed on the first conducting film and an interlayer insulating film, a first diffusion preventing film formed on the second conducting film, a lower electrode film formed on the first diffusion preventing film, and a ferroelectric film formed on the lower electrode film; and a conducting spacer film formed on sidewalls of the lower electrode film, the first diffusion preventing film and the second conducting film.

Ferroelectric memory device guaranteeing electrical interconnection

A process for preparing a hydrophilic polymer film comprising coating a photopolymerization solution which comprises a hydrophilic monomer of lower water swelling ability and a UV stabilizer, on the film surface pre-treated with high frequency, and photopolymerizing the solution so as to improve the hydrophilic property, climate-resistability, and blocking property of the polymer film.

Process for preparing hydrophilic polymer films and apparatus thereof

An apparatus for coating a hydrophilic film which includes a light reaction chamber having UV lamps on either side of the film, two cooling fans and a solvent deflation fan. There are also an air drying plates and coating nozzles.

Growing community of inventors

Kyoungki-do, South Korea

Jae Whan Kim