Metisx Co., Ltd.

Xcena Inc.

Jae Wan Yeon

Ju Hyun Kim

Jin Yeong Kim

Kwang Sun Lee

Do Hun Kim

Gayoung Lee

As one aspect of the present disclosure, an electronic device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor and the volatile memory device, wherein the controller may be further configured to receive a swap-out request for first data in pages from the host processor, generate first compressed data by compressing the first data in response to the swap-out request, and store the first compressed data in the volatile memory device.

Electronic device and computing system including same

As one aspect of the present disclosure, an electronic device is disclosed. The device may include a controller configured to be connected with a host processor and a memory, wherein the controller may be further configured to collect access information indicative of access of the host processor to the memory, and calculate tiering information indicative of accessibility of the host processor to each of a plurality of data units stored in the memory based on the access information.

Electronic device, computing system including same, and memory access monitoring method thereof

The present disclosure relates to a manycore system capable of asynchronous execution of a plurality of threads. The manycore system includes a device memory configured to store data associated with a job requested to be offloaded from a host device, and a plurality of clusters. Each cluster includes a plurality of cores configured to execute a plurality of threads associated with a plurality of tasks included in the job and a management module configured to control asynchronous execution of the plurality of threads by the plurality of cores. Each core includes a plurality of fetch units configured to fetch, from the program memory, instructions associated with threads executed on the cores, one or more execution units configured to execute operations associated with the threads executed on the cores, and a plurality of load and store units configured to load and store data associated with the threads executed on the cores.

Manycore system for performing execution of multi-threads in asynchronous manner

A method for managing threads in a manycore system is launched by one or more processors, and includes receiving, from a host processor, a job descriptor associated with one or more tasks according to an offloading request of the host processor, generating threads for each of the one or more tasks based on the job descriptor, and allocating the generated threads to one or more cores of a cluster that includes a plurality of cores.

Method and apparatus for managing threads in manycore

A byte-addressable electronic device is provided. The electronic device includes a volatile memory device, a mapping table storing address information of the volatile memory device corresponding to address information of a non-volatile storage device, and information indicating whether a command related to data access is processed in relation to the address information of the volatile memory device, and a controller connected to a host processor, the volatile memory device, and the non-volatile storage device, and configured to process commands related to data access received from the host processor based on the mapping table.

As one aspect of the present disclosure, an electronic device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor and the volatile memory device, wherein the controller may be further configured to receive a request related to data access from the host processor, determine whether data corresponding to address information is compressed based on the address information included in the request, and communicate with the volatile memory device and process the request based on a result of determining whether the data is compressed.

A method for translating memory addresses in a manycore system is provided, which is executed by one or more processors, and includes receiving identification information of a thread accessing a memory associated with one or more cores of a cluster that includes a plurality of cores, receiving a virtual address of data accessed by the thread, and determining a physical address of data in the memory based on the virtual address and the identification information of the thread.

Growing community of inventors

Yongin-si, South Korea

Jae Wan Yeon