Samsung Electronics Co., Ltd.

Konkuk University Industrial Cooperation Corp

Jae-Sup Lee

Seong-soo Lee

Seung-woo Kim

Kang-yoon Lee

Tae-Wook Kim

Hyun-Il Kang

Dong-Hyun Lee

Sang-Hyun Woo

Choong-yul Cha

Joon-Sung Park

Young-Gun Pu

An-Soo Park

Young-Hwan Kim

Jong-Ae Park

Chang-Seok Lee

Jeong-Hoon Lee

Song-cheol Hong

Kwy-ro Lee

Ju-Hyun Ko

Eun-chul Park

Jae-Kon Lee

Sung-nam Kim

Sung-sik Song

Holger Lothar

Dong-Hyun Baek

Kang-Yoon Lee

Hyun-Ii Kang

A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.

Digital phase locked loop device and method in wireless communication system

A Time-to-Digital Converter (TDC) is provided. The TDC includes a first TDC unit for receiving a first input signal and a second input signal, delaying the first input signal on a specific time basis using each of first delay blocks, generating first phase-divided signals by performing first phase division on signals of input/output nodes for each of the first delay blocks on a predefined Phase-Interpolation (PI) delay time basis, and outputting the second input signal and a phase-divided signal closest to the second input signal, among the first phase-divided signals, a time amplifier for independently time-amplifying the second input signal and the phase-divided signal closest to the second input signal, and a second TDC unit for delaying a phase-divided signal closest to the time-amplified second input signal on a specific time basis using each of second delay blocks, and generating second phase-divided signals by performing second phase division on signals of input/output nodes for each of the second delay blocks on a predefined PI delay time basis.

Time-to-digital converter and operation method thereof

Provided is a polar transmitter which increases a modulation rate using a multi-phase generator and includes: a data processor which processes and separates incoming data to an amplitude component and a phase component; a multi-phase generator which generates a plurality of carriers having a plurality of phase components by processing a carrier having a certain frequency; a selection output part which selects and outputs a carrier having a phase substantially equal to the phase component; and a carrier output part which synthesizes the output carrier with the amplitude component and outputs a carrier. Accordingly, the modulation rate of the carrier can be increased and the bandwidth can be extended with the related art polar transmitter. Therefore, the polar transmitter is applicable to the wideband communications, the multi-mode, and the multi-band.

Polar transmitter for increasing modulation rate using multi-phase generator

A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

Digital frequency detector and digital phase locked loop using the digital frequency detector

Disclosed is a method and an apparatus for self-calibrating direct current (DC) offset and imbalance between orthogonal signals, which may occur in a mobile transceiver. In the apparatus, a transmitter of a mobile terminal functions as a signal generator, and a receiver of the mobile terminal functions as a response characteristic detector. Further, a baseband processor applies test signals to the transmitter, receives the test signals returning from the receiver, and compensates the imbalance and DC offset for the transmitter side and the receiver side by using the test signals.

Method and apparatus for self-calibration in a mobile transceiver

A wire-stacked transformer has a first loop supplied with electric power and built with one or more metal plates forming a magnetic field, a second loop disposed in a concentric circle with the first loop and generating induction current, and loop wires disposed between the respective metal plates of the first loop and supplying electric power to each metal plate. Accordingly, efficiency of a power amplifier can be enhanced by reducing the loss of the DAT.

Wire-stacked transformer

A diode circuit having a passive element property, and an impedance modulator and a direct current (DC) source that use the diode circuit are provided. The diode circuit includes a first diode that generates a predetermined DC and alternating currents (AC) when a radio frequency (RF) signal is applied; and a DC path that is connected in parallel to the first diode, forms a predetermined loop and circulates the DC current within the loop. The DC path includes an inductor or an LC parallel resonator. The DC path includes a second diode that is disposed in the opposite direction to the first diode and connected to the first diode in parallel. The present invention can relieve difficulty in designing an RF circuit.

Diode circuit having passive element property, impedance modulator including the diode circuit, and DC source including the diode circuit

A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.

High resolution time detecting apparatus using interpolation and time detecting method using the same

An inductor with plural coil layers includes a base wafer; a plurality of insulating layers sequentially laminated on one surface of the base wafer; and a plurality of coil layers built in the plurality of insulating layers, respectively, and having different magnetic flux passage areas.

Inductor with plural coil layers

A digital to analog converter (DAC) is provided. The DAC includes a first loop unit to receive a plurality of sources and comprising a plurality of primary winding of transistors formed at a plurality of locations, and a second loop unit comprising secondary windings to correspond to the primary windings, to receive the plurality of sources through the first loop unit, and combine the plurality of sources and output the result. Accordingly, a DAC is capable of directly converting a digital signal into an RF analog signal.

Digital-to-analog converter (DAC)

A shredded parallel stacked inductor is provided. The shredded parallel stacked inductor includes a substrate, an oxide film formed on the substrate, metallic layers spirally formed within the oxide film, and vias formed in regions of the metallic layers to join the metallic layers in parallel, thus forming a spiral cavity in a center part of the metallic layers.

Shredded parallel stacked inductor

A variable degeneration impedance supply circuit, including: two alternatively connected transistors; a capacitor circuit having a predetermined capacitance and serially connecting output terminals of the two transistors; and a switch for controlling on/off state between the capacitor circuit and the output terminal, according to a predetermined first control signal. The circuit further includes: at least one sub capacitor circuit arrayed in parallel to the capacitor circuit for serially connecting the output terminals of the two transistors; and at least one sub switch for controlling on/off state between the sub capacitor circuit and the output terminal, according to a predetermined control signal. Therefore, the magnitude of a degeneration impedance can be varied by controlling degeneration capacitance. Moreover, the variable degeneration impedance supply circuit can be advantageously applied to a voltage controlled oscillation circuit and a frequency divider circuit.

Variable degeneration impedance supply circuit using switch and electronic circuits using the same

Provided are an on-chip balun, a transceiver using the on-chip balun, and a method for fabricating the on-chip balun. The on-chip balun includes: a first metal winding including a port grounded and a port to which an unbalanced signal is input; a second winding outputting an induced current generated by the first metal winding as two signals having about equal intensity and a phase difference of about 180&#xb0;; and a ground shield positioned between the first and second metal windings and having a symmetric structure so as to generate a symmetric parasitic capacitance between the ground shield and the second metal winding. The ground shield can be inserted between the first and second metal windings to remove an asymmetrical parasitic capacitance so as to reduce a phase imbalance and a gain imbalance of an output value of the second metal winding. As a result, a highly balanced on-chip balun can be fabricated.

On-chip balun and transceiver using the same and method for fabricating on-chip balun

A predistorter that linearizes the nonlinearity of a power amplifier in a system supporting a multimode and a multiband (frequency band). The predistorter includes a field-effect transistor, an impedance transform unit, a first inductor, a first capacitor, and a second capacitor. The field-effect transistor has a source connected to the ground and uses a variable gate bias voltage. The impedance transform unit is connected to a drain of the field-effect transistor to perform impedance transform. The first inductor is connected between the impedance transform unit and a voltage provided to the field-effect transistor. The first capacitor is connected between a power input terminal and the impedance transform unit. The second capacitor is connected between a power output terminal and the impedance transform unit.

Predistorter for power amplifier

A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

Growing community of inventors

Yongin-si, South Korea

Jae-Sup Lee