Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Lg Philips Lcd Co., Inc.

Jae-Sung Yu

Seok-Woo Lee

Youngwook Kim

Kui-Yon Mun

Jin-Hyeok Choi

Soong-Mann Shin

A storage device includes a memory device configured to store data and a memory controller connected to the memory device through a data strobe line and a plurality of data lines. The storage device adds a predetermined specific pattern in front of data and processes data input following the specific pattern as valid data during a read or write operation. The specific pattern is provided in alignment with a data strobe signal (DQS) latency cycle. The memory controller detects a specific pattern input from the memory device during a read operation and processes data input following the specific pattern as valid data when the detected specific pattern matches an internally stored specific pattern.

Storage device communicating with specific pattern and operating method thereof

A storage device includes a nonvolatile memory and a memory controller. The nonvolatile memory performs read, write, and erase operations. The memory controller operates in an operating mode where the memory controller exchanges a voltage signal, set to a reference voltage level within an allowable range, with the nonvolatile memory or receives the voltage signal from an external device. When operating in the operating mode, the memory controller optimizes an operating frequency of the nonvolatile memory depending on a voltage level of the voltage signal and a temperature.

Storage device and controlling method thereof

A method of programming a multilevel cell flash memory includes dividing a memory cell array of the flash memory into a user block and a cache block, programming first LSB data into a page of the user block, programming first MSB data into the page of the user block after programming the first LSB data, programming second LSB data into a page of the cache block, and storing control data for controlling the flash memory in the cache block.

Programming methods of memory systems having a multilevel cell flash memory

A multi-channel type thin film transistor includes a gate electrode over a substrate extending along a first direction, a plurality of active layers parallel to and spaced apart from each other extending along a second direction crossing the first direction, and source and drain electrodes spaced apart from each other with respect to the gate electrode and extending along the first direction, wherein each of the plurality of active layers includes a channel region overlapped with the gate electrode, a source region, a drain region, and lightly doped drain (LDD) regions, one between the channel region and the source region and another one between the channel region and the drain region, wherein the LDD regions of the adjacent active layers have different lengths from each other.

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Seoul, South Korea

Jae-Sung Yu