Samsung Electronics Co., Ltd.

Korea University Industrial Academic Collaboration Foundation

Korea University Research and Business Foundation

Jae-Sung Rieh

In-sang Song

Byeoung-ju Ha

Byeong-kwon Ju

Jea-shik Shin

Young-Min Park

Jin-Woo Lee

Yun-kwon Park

Duck Hwan Kim

In Sang Song

Ho Soo Park

Byeong Kwon Ju

Sang Uk Son

Jea Shik Shin

Jung Soo Kim

Jungsoo Kim

Sung-woo Hwang

Jae Hyeon Park

Hee-Tae Kim

Kyung Jin Lee

Do Yoon Kim

Dong Hoon Hwang

DoYoon Kim

Yong-Kyu Kim

Daekeun Yoon

Jae Shik Shin

Yong Ho Oh

Yun-Kwon Park

Sue Yeon Kim

Jung-Hwan Yoo

Ki Ryong Song

Jai Heon Cho

Seung Yong Lee

Disclosed is a high frequency beam forming device. The high frequency beam forming device includes a 2D radiation array structure unit in which oscillators coupled to antennas are arranged in 2D; and a plurality of phase difference detectors coupled between the oscillators formed in the 2D radiation array structure unit to detect a phase difference between the coupled oscillators.

High frequency beam forming device

Disclosed is an ultra low power transimpedance amplifier based on spintronics. According to the present invention, provided is an ultra low power transimpedance amplifier based on spintronics, which includes: a spintronics based oscillator receiving current and outputting an alternating signal by using spin transfer torque or spin orbit torque; a bandpass filter passing a signal in a predetermined frequency band of the alternating signal output by the spintronics based oscillator; and a spintronics based detector outputting voltage by inputting the signal in the predetermined frequency band, which is output by the bandpass filter.

Ultra low power transimpedance amplifier based on spintronics

The present invention relates to a multi-chip detector apparatus composed of multiple single detectors. An embodiment of the invention provides a multi-chip detector apparatus having a multiple number of single chips arranged in inter-chip connection on a substrate, where the multi-chip detector apparatus includes: a first single chip that has a multiple number of single detectors formed in m rows and n columns; a second single chip that is positioned at either a left side or a right side of the first single chip and is connected row-wise with the first single chip; and a third single chip that is positioned at either an upper side or a lower side of the first single chip and is connected column-wise with the first single chip, and where the second single chip and the third single chip also have multiple numbers of single detectors formed in m rows and n columns.

Multi-chip detector appratus

A device and a method for reducing an influence of interference between signals using an aperture array in chip-to-chip wireless communication are provided. The device includes a transmitter including at least one transmission antenna for transmitting a signal, a receiver including at least one reception antenna for receiving the signal, a guide structure including at least one opening for guiding a path of the signal, and the at least one transmission antenna, the at least one reception antenna, and the at least one opening are arranged to correspond to one another.

Method for providing chip-to-chip wireless communication and electronic device thereof

A frequency locked loop is disclosed. The disclosed frequency locked loop may include: a voltage-controlled oscillator configured to output a LO signal; a mixer configured to mix an RF signal with the LO signal to output an IF signal; a first IF path part configured to transfer the IF signal; a second IF path part configured to transfer the IF signal; and an error amplifier configured to receive output signals of the first IF path part and output signals of the second IF part as input, where the voltage-controlled oscillator adjusts a frequency of the LO signal based on an output signal of the error amplifier, the first IF path part has the conversion gain decreased according to an increase in the frequency of the IF signal, and the second IF path part has the conversion gain increased according to an increase in the frequency of the IF signal.

Frequency locked loop of a heterodyne structure

A method of fabricating a nano resonator, includes forming a line pattern in a first substrate, and transferring the line pattern to a second substrate including a gate electrode. The method further includes forming a source electrode and a drain electrode on the transferred line pattern.

Apparatus and method for fabricating nano resonator using laser interference lithography

A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode and configured to vibrate in the presence of the magnetic field. The nanowire includes a protruding portion extending in a direction of the gate electrode.

Nano resonance apparatus and method

A resonator fabrication method is provided. A method includes providing a plurality of electrode patterns disposed apart from each other on a substrate using a nano-imprint technique; and forming an extended electrode pattern connected to a plurality of electrode patterns, and forming a nano structure laid across an extended electrode patterns. Therefore, a nano-electromechanical system (NEMS) resonator is easily fabricated at a nanometer level.

Resonator and fabrication method thereof

A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.

Resonant structure comprising wire and resonant tunneling transistor

A MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, includes: gate insulating layers arranged at equal intervals in the form of a (n&#xd7;m) matrix, and a gate electrode placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire, which is electrically connected to the gate contact; source/drain contacts arranged at equal intervals in a matrix to form apexes of a square centered at the gate electrode and contact a doping region except for the bottom of the gate insulating layers; and a second metal wire, which is electrically connected to the source/drain contacts.

MOS varactor and fabricating method of the same

Growing community of inventors

Seoul, South Korea

Jae-Sung Rieh