Samsung Electronics Co., Ltd.

Jae-Sun Yun

Jin-Hyun Shin

Joon-Hee Lee

Jang-Gn Yun

Hoo-Sung Cho

Jin-hyun Shin

Sang-youn Jo

Seong-soo Kim

Jin-Yong Oh

Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.

Semiconductor device having interconnection line

The nonvolatile memory device may include a substrate including a first region and a second region. A string line group may be disposed on the substrate in the first region, and a bias interconnection group may be disposed above the substrate in the second region. The bias interconnection group may include a string select bias interconnection, cell bias interconnections, and a ground select bias interconnection, which may be respectively electrically connected to a string select line, word lines, and a ground select line of the string line group. The string select bias interconnection may be disposed between the ground select bias interconnection and the cell bias interconnections of the bias interconnection group.

Nonvolatile memory device

A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

Method of applying wire voltage to semiconductor device

Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.

Trench isolated integrated circuit devices including grooves

Gate structures of a non-volatile integrated circuit memory device can include a thermal oxidation layer on a substrate beneath the gate structure that defines a side wall of the gate structure. An oxygen diffusion barrier layer is on the side wall of the gate structure and a floating gate is on the thermal oxidation layer and has a curved side wall portion. Related methods are also discussed.

Growing community of inventors

Gyeonggi-do, South Korea

Jae-Sun Yun