Daewoo Telecom Ltd.

Jae-Sul Ha

Sang-Yong Lee

An apparatus for use in a synchronous transmission system, for detecting a failure of a clock signal, which comprises: a reference clock generator for generating a reference clock signal (RCS) in response to a reset signal issued by a system controller in the STS; and means for receiving a clock signal, the RCS issued by the reference clock signal generating means and the reset signal and for producing a failure signal for the received clock signal, wherein the failure represents a state of a clock in which the clock does not have a pulse for a predetermined time interval, the time interval being measured by using the RCS.

Apparatus for detecting clock failure for use in a synchronous

An apparatus is used for mapping digital signal data in a data packet of a packet clock having a plurality of clock pulses wherein the data packet is composed of information data and the digital data. The ratio of the number of bits of the information data with respect to the number of bits in the data packet is M/N with M and N being positive integers and the information data includes overhead data bits and one or more data bits. The apparatus comprises a counter for counting the clock pulses to provide counted values; a gapping signal generator for generating gapping control signals based on the counted values and the ratio M/N, wherein an M number of gapping control signals are generated for every N clock pulses; and gapping device for finding overhead data bits among the information data and gapping clock pulses corresponding to the overhead data bits in response to the gapping control signals.

Mapping apparatus for use in a synchronous multiplexer

An apparatus for use in a synchronous transmission system (STS) efficiently tests N clock signals provided from a device incorporated in the STS, wherein N is a positive integer larger than 1 and the N clock signals are represented by a first predetermined clock frequency. The N clock signals are first received by a counting device in response to a reset signal issued by a system controller in the STS to produce an error reference signal for each of the N received clock signals. And then, at a clock generator, a reference clock signal represented by a second predetermined clock frequency is provided. A first set of error detection signals for the N clock signals is derived based on the N clock signals, the reference clock signal and the error reference signals at a first error detection device. Thereafter, at a second error detection device, a second set of error detection signals for the N clock signals is obtained based on the reference clock signal and the error reference signals. Finally, the first and the second sets of error detection signals are logically combined at an error decision device to thereby produce information representing the status of each of the N clock signals.

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Incheon, South Korea

Jae-Sul Ha