Samsung Electronics Co., Ltd.

Jae-Sop Kong

Dong-Han Lee

Sung-Chul Yoon

Min-Soo Kim

Kee-Moon Chun

Jong-ho Roh

Sung-Hoo Choi

Yong-Ki Byun

Eun-Ji Kang

An image processor comprises first scaling logic that receives image data comprising a first number of lines and generates first scaled image data by scaling down the image data in a first direction, a rotation buffer that has storage capacity for storing a second number of lines less than the first number of lines and stores the first scaled image data in a rotated state, and second scaling logic that generates second scaled image data by scaling down the first scaled image data in a second direction different from the first direction.

Image processor, for scaling image data in two directions. Computing system comprising same, and related method of operation

A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device.

Display controller and display system including the same

A reconfigurable image scaling circuit includes a horizontal scalar, a bufferer, and a vertical scalar. The horizontal scalar is configured to generate a horizontally scaled image data by scaling an input image data horizontally. The bufferer includes a mapper and a plurality of buffers. The plurality of the buffers are configured to store the horizontally scaled image data. The vertical scalar is configured to generate an output image data by scaling the horizontally scaled image vertically using a vertical scaling method.

Reconfigurable image scaling circuit

An application processor includes a memory controller, a display block and a power management unit. The memory controller controls an external memory that stores an image signal to be displayed on a display unit. The display block includes an internal frame buffer and a display controller and the display controller controls the image signal to be displayed on the display unit. The power management unit adaptively controls a power mode of the application processor based on a characteristic of the image signal to be displayed and a power control overhead index.

Application processors, mobile devices including the same and methods of managing power of application processors

A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.

System-on-chip and method of operating the same

Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

System-on-chip having special function register and operating method thereof

In one embodiment, the converter is configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal. The second sync signal is for controlling image sensing.

Apparatuses, systems, and methods for converting a display driver sync signal into an image sensor sync signal

In a self-diagnosing method of a volatile memory device, a processor outputs a self-refresh entrance command and enters a power save mode, and a volatile memory device performs a self-diagnosing operation for a plurality of memory cells in response to the self-refresh entrance command while the processor is in the power save mode.

Self-diagnosing method of a volatile memory device and an electronic device performing the same

A first-in first-out (FIFO) memory device includes a main FIFO unit, an auxiliary FIFO unit and a control unit. The main FIFO unit includes first through N-th one-port memories, each of which including M entries, where N and M are integers greater than or equal to two. The auxiliary FIFO unit includes one dual-port memory having M entries. The control unit performs a write operation by receiving a write command and data and storing the data in one of the main FIFO unit and the auxiliary FIFO unit based on an operating mode, and performs a read operation by receiving a read command and reading the data from one of the main FIFO unit and the auxiliary FIFO unit based on the operating mode.

Growing community of inventors

Gwacheon-si, South Korea

Jae-Sop Kong