Samsung Electronics Co., Ltd.

Jae-Seung Choi

Sang-Yeop Baeck

Dong-Wook Seo

Hoon Bae Kim

Tae-Hyung Kim

Taejoong Song

Tae-hyung Kim

Jisu Yu

Inhak Lee

Hyunsu Choi

Daeyoung Moon

Dae-young Moon

In-Hak Lee

Jung-Myung Kang

Sun-Yung Jang

Hyun-Su Choi

Jung-Ho Do

Sang-shin Han

Siddharth Gupta

Jae-hyun Lim

Tae-Joong Song

Jong-Hoon Jung

Chan-Ho Lee

Gyu-Hong Kim

Dong-Sub Kim

Tae-joong Song

Jung-Hun Heo

Sung-Hyun Park

Jong-pil Lee

In-Gyu Park

Sil-Kuy Lim

Soung-Hoon Sim

Su-Hyun Yun

A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Semiconductor device for selectively performing isolation function and layout displacement method thereof

Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

Integrated circuit having heterogeneous gate contacts over active regions

A memory device includes a memory cell array and a peripheral circuit. The memory cell array receives a first power supply voltage and includes a plurality of bit cells that store data based on the first power supply voltage. The peripheral circuit is receives a second power supply voltage and controls the memory cell array based on the second power supply voltage. The peripheral circuit includes a voltage generation circuit that receives the first power supply voltage and the second power supply voltage. The voltage generation circuit adaptively adjusts a word-line driving voltage directly or indirectly based on a difference between the first power supply voltage and the second power supply voltage during a memory operation on the plurality of bit cells, and applies the word-line driving voltage to a first word-line coupled to first bit cells selected from the bit cells.

Memory device system-on-chip including the same and method of operating the same

Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

Voltage control circuit including assist circuit and memory device including the same

Integrated circuit having heterogeneous source/drain and gate contacts

Layout of semiconductor device for selectively operating as insulating circuit or driving circuit

A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.

Memory devices and methods of operating the same

A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Volatile memory device and system-on-chip including the same

An integrated circuit, a method of controlling an operation timing of a memory device, an application processor, and a power manager are provided. The application processor includes: a power manager configured to determine a first operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the first operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal; and a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, wherein the power manager is configured to provide the first operating power level to the first memory device.

Memory device of adaptively calibrating timing margin and integrated circuit including the same

A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

Negative voltage generator and semiconductor memory device

A Liquid Crystal Display (LCD) module for use in a portable terminal is provided. The LCD module includes a reinforcement plate of a metal material having a bottom surface, and a side surface bent and extended at a substantially constant height along an edge from the bottom surface, a backlight unit laminated onto an upper part of the reinforcement plate, and having a frame of a synthetic resin material that is formed along an edge to insert-mold the reinforcement plate, and an LCD panel fixed by a double sided tape at an upper part of the backlight unit. A portion of the side surface of the reinforcement plate is sequentially twice bent back onto itself on the outside of the reinforcement plate such that its end has a substantially constant width in contact with the bottom surface of the reinforcement plate.

Liquid crystal display module for portable terminal

Growing community of inventors

Hwaseong-si, South Korea

Jae-Seung Choi