Goldstar, Co., Ltd.

Lg Semicon Co., Ltd.

Goldstar Electron Co., Ltd.

Inha University Foundation

Samsungsdsco.,ltd.

Jae S Jeong

Min Hwa Park

Do Hyoung Kim

Hun Hur

Mi Ran Kim

Nam Soo Jeon

Soon Hyoung Hwang

Beam-Hoan O

Won Kyoung Kim

Se-Geun Park

Chul Ho Kim

Se Hyuk Noh

Joo Hee Choi

A device-to-device (D2D) communication method is provided. According to an inventive concept, the method comprises, storing, by a first device, first authentication data including a hash chain, which is a sequential concatenation of hash values, and storing, by a second device, second authentication data including an initial hash value of the hash chain, transmitting, by the first device, a final hash value of the hash chain to the second device, determining, by the second device, whether authentication between the first and second devices has succeeded by repeatedly hashing the initial hash value stored in the second device until a hash value identical to the final hash value is returned, and if a determination is made that authentication between the first and second devices has succeeded, performing, by the first and second devices, a connection establishment process for establishing a connection between the first and second devices.

Device-to-device communication method including device-to-device authentication using hash chain

An enhanced inductively coupled plasma reactor which comprises; a chamber; a power supply for providing radio-frequencies necessary to generate plasma within the chamber; an antenna for producing electric fields and magnetic fields with a radio-frequency power from the power supply to generate plasma within the chamber; Helmholtz coils for shaking the plasma with intermittent modulation of a weak magnetic field to increase the density of the plasma and decrease the electron temperature and enhance the uniformity of the plasma, the Helmholtz coils consisting of two coils which are symmetrically arranged with a common axis, winding around the chamber at an upper position and a lower position, respectively, the weak magnetic field being produced by providing a combination of a direct current and an alternating current to the Helmholtz coils; a wafer stage and support; a bias RF power supply for controlling ion energies, connected to the wafer stage; and a matching box for optimally controlling and transferring the power from the bias RF power supply. Axis-directed magnetic fields which vary with time are formed by the provision of the combination of the currents. When they are controlled in various cycles, the plasma can be effectively shaken and a resonant effect occurs, thereby increasing the ion density and decreasing the electron temperature.

Enhanced inductively coupled plasma reactor

A method for treating the surface of a silicon substrate, which has been subjected to a dry etching process, including applying an electron cyclotron resonance process to the exposed surface to thereby etch away a thin layer of the exposed surface. The ECR etching process is preferably conducted in an SF.sub.6 --O.sub.2 gas mixture and the thickness of the thin layer is no greater than 500 .ANG.. The silicon wafer damaged and contaminated by the dry etching processes can be repaired to the level of virgin, bare silicon wafer by this method. This silicon wafer treatment method allows the semiconductor device thereby fabricated to have improved operating characteristics. For example, the leak current generated in a semiconductor device fabricated on the silicon wafer which has undergone the present treatment is markedly diminished to approximately one-tenth of the leak current generated in the semiconductor device fabricated on the silicon wafer which has not undergone this treatment.

Method for treating the surface of silicon substrate post dry etching

A method for fabricating a semiconductor memory device including a matrix of memory cells each constituted by one transistor and one capacitor and capable of obtaining a large capacitance for achieving a high integration and yet maintaining superior characteristics of its elements. The method includes the steps of: (a) forming a transistor gate electrode in a portion of an insulating layer formed over a semiconductor substrate, in a buried manner; (b) forming a trench in the semiconductor substrate through a portion of the insulating layer; and (c) forming a transistor channel region, a source, a drain and a capacitor storage node, as a single layer, over a region defined over a transistor gate electrode-buried portion of the insulating layer and a region defined in the trench. Thereby a source, a drain and a gate channel of each transistor and a capacitor storage node are formed by a single layer. With this structure, a minimum information transmitting path is obtained, thereby enabling the overall structure and the fabrication therefor to be simplified. Furthermore, this method makes it easy to form an active region where elements are formed, without using an element isolation process, and thus overall fabrication becomes simplified.

Method for fabricating semiconductor memory devices

A semiconductor device and a method of making the same capable of simplifying the process of making and reducing the cost of making. In the method a first layer is formed which has a plurality of conductors at its edge portion. Thereafter, a second layer is formed on the first layer which is to be selectively etched to form a pattern. During the etching, current is detected from the conductors and the etching is stopped dependent on the current detected from the conductors. The semiconductor device includes a transparent electrode on a substrate the transparent electrode having protrusions which have a top surface. A first insulation layer exists between the protrusions. There is a color emitting layer on the top surfaces of the protrusions and the insulation layer. The method includes the steps of:

Method of making a semiconductor device

A DRAM cell and a method for fabricating the same capable of obtaining a large capacitance for achieving a high integration and yet maintaining superior characteristics of elements. A capacitor structure is provided, which includes a common storage node formed at the inner wall of a trench, and two plate electrodes connected to each other in parallel, that is, a substrate and a polysilicon layer formed over the storage node via a second dielectric film and connected to the substrate in parallel. With such a capacitor structure, the capacitance per unit capacitor area can be maximized. A source, a drain and a gate channel of each transistor and a capacitor storage node are formed by a single layer. With this structure, a minimum information transmitting path is obtained, thereby enabling the overall structure and the fabrication therefor to be simplified. Furthermore, the present invention makes it easy to form an active region where elements are formed, without using an element isolation process. Accordingly, overall fabrication becomes simplified.

Semiconductor memory device and method for fabricating the same dynamic

A semiconductor device and a method of making the same capable of simplifying the process of making and reducing the cost of making. In the method a first layer is formed which has a plurality of conductors at its edge portion. Thereafter, a second layer is formed on the first layer which is to be selectively etched to form a pattern. During the etching, current is detected from the conductors and the etching is stopped dependent on the current detected from the conductors. The semiconductor device includes a transparent electrode on a substrate the transparent electrode having protrusions which have a top surface. A first insulation layer exists between the protrusions. There is a color emitting layer on the top surfaces of the protrusions and the insulation layer.

Multicolored electric field light emitting device with protruded

Methods of making semiconductor memory cells and semiconductor memory devices capable of improving the degree of integration and simplifying the overall manufacturing processes. Within a substrate made of a semiconductor material or an insulating material, at least one trench is formed to provide a capacitor region. In the trench are formed a plate electrode, a capacitor dielectric layer and a storage node electrode which constitute a capacitor. The semiconductor substrate may be used as the plate electrode. In this case, the trench has only the capacitor dielectric layer and the storage node electrode. At the inlet of the trench filled with the constituting elements of the capacitor, a gate electrode and a semiconductor layer as an active layer are formed to extend vertically perpendicular to the trench inlet. A bit line contact is formed on the semiconductor layer. Over the bit line contact are formed a bit line contact and a bit line, in this order.

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Seoul, South Korea

Jae S Jeong