Samsung Electronics Co., Ltd.

Jae-ryong Jung

Kyoo-chul Cho

Sam-jong Choi

Kyung-soo Kim

Tae-soo Kang

Sang-Sig Kim

Yong-kwon Kim

Jin-Sung Kim

Gwang-Seon Byun

Hong-Shik Kim

Hee-Kyeong Jeon

Chang-Hyuk Ok

Yong-Jun Min

Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Integrated circuit device gate structures

A fuse of a fuse box includes a fuse line with a plurality of sub-fuse lines. A fuse cutting method involves selectively cutting sub-fuse lines of a fuse line.

Fuse box, method of forming a fuse box, and fuse cutting method

Methods of forming integrated circuit device gate structures

Growing community of inventors

Gyeonggi-do, South Korea

Jae-ryong Jung