Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Jae-Rim Lee

Myung-Soo Jang

Jong-Wha Chong

Cheol-Jon Jang

Jae-Hwan Kim

Min-Beom Kim

Byung-Gyu Ahn

Wen Rui Li

To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.

Method of designing power supply network

A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.

Method of designing arrangement of TSV in stacked semiconductor device and designing system for arrangement of TSV in stacked semiconductor device

Growing community of inventors

Hwaseong-si, South Korea

Jae-Rim Lee