Samsung Electronics Co., Ltd.

Jae-pil Shin

Jong-won Kim

Moon-hyun Yoo

Tae-hyun Kim

Jin-kyu Park

Moon-Hyun Yoo

Jong-Bae Lee

Tae-heon Kim

Yong-hyeon Kim

Young-ile Kim

Jin Hwan Choi

Sang-ho Park

In-Sung Kim

Young-Mi Lee

Yoonna Oh

Jong-bae Lee

Won-Young Chung

Ho-Joon Lee

Kyu-Baik Chang

Byoung-Sup Ahn

Jin-sook Choi

Ji-soong Park

Kwang-jai Yoo

Chang-Woo Kang

Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.

Systems and methods of fabricating semiconductor devices

A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

Methods of detecting stresses, methods of training compact models, methods of relaxing stresses, and computing systems

A method of correcting flare includes measuring flare of a test pattern, calculating point spread functions (PSFs) of the flare as a function of distance, and correcting the flare using corresponding PSFs for an influence range of the flare. The influence range is divided into a first range less than a predetermined distance and a second range equal to or greater than the predetermined distance, and corresponding PSFs are separately applied to the first and second ranges to correct the flare.

Method of correcting flare and method of preparing extreme ultra violet mask

In a method of inspecting a mask, an image of a pattern on the mask may be obtained. A histogram of the image by grey levels may be obtained. The histogram may be compared with information of the pattern to detect a defect of the mask. Thus, reliability of defect detection in the mask may be remarkably improved.

Method of inspecting a mask

A mask set with a light-transmitting region of a controlled size includes a plurality of masks for performing in-situ synthesis on probes of a microarray, wherein each mask includes a light-transmitting region and a light-blocking region, and the size of the light-transmitting region is equal to or greater than about 5% of the total size of the light-transmitting and light-blocking regions.

Mask set for microarray, method of fabricating mask set, and method of fabricating microarray using mask set

Provided are a method and apparatus for designing a fine pattern that can be entirely transferred onto an object. The method includes reading the original data of a fine pattern for exposure. The fine pattern is divided into a first pattern not requiring revision and a second pattern requiring revision. The fine pattern is revised by forming an auxiliary pattern maintaining a first distance Dfrom the second pattern. A fine pattern to be transferred onto a target object is estimated by running an emulation program including a first auxiliary pattern and a second auxiliary pattern. The estimated fine pattern is compared to the original data of the fine pattern for exposure, and the revised fine pattern is designated as a final fine pattern if there is no difference between the estimated fine pattern and the original data of the fine pattern for exposure.

Method and apparatus for designing fine pattern

In a mask for forming a fine pattern to completely transfer a first and a second pattern from the mask onto a receiving object, and a method of forming the mask, the mask includes a first pattern, a second pattern, and a supplemental pattern. The first pattern repeats in a first direction. The second pattern is arranged between and parallel to the first pattern and has a first width W. The supplemental pattern is disposed between the first pattern and the second pattern, and is spaced apart by a first distance Din the first direction from the second pattern.

Mask for forming fine pattern and method of forming the same

Dummy patterns are generated for a region of an integrated circuit that is divided into buckets by obtaining a local pattern density for a respective bucket and adjusting a density of the dummy pattern for the respective bucket as a continuously variable function of the respective local pattern density and a target density for the region. By providing a continuously variable dummy pattern density, the desired density of the dummy pattern group may be adjusted precisely, to thereby reduce or eliminate loading effects. The density of the dummy pattern for the respective bucket may be calculated according to a formula in which the density of the dummy pattern is continuously variable. The dummy patterns may include features of fixed pitch and a size of the features of fixed pitch is increased or decreased as a continuously variable function of the respective local pattern density and the target density for the region.

Continuously variable dummy pattern density generating systems, methods and computer program products for patterning integrated circuits

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Suwon-si, South Korea

Jae-pil Shin