Skhynix Inc.

Jae Min Lee

Min Ho Her

Seung Il Kim

Yong Ho Kim

Seon Young Choi

Dong Hyun Kim

Sung Ho Kim

Geu Rim Lee

Myoung Kyun Kim

Won Gyu Park

A memory device configured to select a page having a probability that uncorrectable error correction codes (UECC) will occur by comparing a reference current with a sensing current, and configured to perform a read reclaim operation or an additional pulse applying operation on the corresponding page according to the comparison.

Memory device and operating method of the memory device

The present technology relates to a storage device and a method of operating the same. The storage device includes a memory controller configured to generate and output a get parameter command set, including normal addresses and a dummy address, during a parameter read operation, and a memory device configured to, in response to the get parameter command set, read parameter data that is stored in a CAM block and store the read parameter data in target registers corresponding to the normal addresses. The memory device stores dummy data in a dummy register corresponding to the dummy address.

Storage device and method of operating the same

The present disclosure relates to an electronic device. A storage device includes a memory device configured to include a plurality of memory cells and a memory controller configured to determine a read voltage for a read operation to be performed on the memory device according to whether the read operation is a cache read operation.

Storage device and operating method thereof

The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of memory blocks, the memory device configure to perform on each of the plurality of memory blocks at least one of a program operation, a read operation, or an erase operation in response to an internal command; and a controller in communication with a host and the memory device and configured to receive a request from the host and generate the internal command in response to the request from the host, the controller further configured to control the memory device to perform a stress check operation on a first memory block of the plurality of memory blocks in which the program operation has been completed.

Memory system and method of operating memory system

Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory device including a plurality of memory blocks, each memory block including a plurality of memory cells coupled to a plurality of corresponding word lines; and a memory controller configured to store data in memory cells included in a main area coupled to a selected word line of the plurality of word lines, and store word-line information in a spare area coupled to the selected word line to indicate that a program operation has been performed on the main area.

Storage device and method of operating the same for detecting last programmed page

Provided herein may be a memory device, a memory system having the memory device, and a method of operating the memory device. The memory device may include a memory cell array configured to store data, a peripheral circuit configured to perform a program operation on the memory cell array, and a control logic configured to perform the program operation by controlling the peripheral circuit and to perform a status check operation after the program operation. Here, the control logic may be configured to, based on a determination that the status check operation has passed, perform a number-of-program pulses comparison operation by comparing a number of program pulses used in the program operation to a first preset range.

Growing community of inventors

Cheongju-si, South Korea

Jae Min Lee