Samsung Electronics Co., Ltd.

Jae-kyu Lee

Jonghyun Go

Gwan-Hyeob Koh

Ki-seok Suh

Yoo-Sang Hwang

Hyeong-sun Hong

Sung-woo Kim

Dae-Won Kim

JungChak Ahn

Seung-sik Kim

Min-Woong Seo

Jae-Goo Lee

Young-chan Kim

Dae-Hwan Kang

Prasad Basavaraj Dandra

Vijay Ganesh Surisetty

Hyuk-Soon Choi

Kyung-rok Kim

Siddhi Chandrashekhar Mayekar

Akshay Rastogi

Sung-In Kim

Song-yi Kim

Sung-in Kim

An image sensor for securing an area of a photodiode includes a pixel area and a transistor area adjacent to the pixel area. The pixel area may include a photodiode and a floating diffusion area. The transistor area may include transistors extending along an edge of the pixel area. The transistors in the transistor area may include a reset transistor, one or more source follower transistors, and one or more selection transistors, and the reset transistor and one source follower transistor adjacent to the reset transistor may share a common drain area. The source follower transistors and the selection transistors may each share a common source area or a common drain area between two adjacent transistors thereof.

Image sensors

An image sensor device includes a digital pixel that includes a photo detector, a comparator, and a memory circuit, a pixel driver that controls the digital pixel, and a digital logic circuit that performs a digital signal processing operation on a digital signal output from the digital pixel. The photo detector and a first portion of the comparator are formed in a first semiconductor die, a second portion of the comparator, the memory circuit, and the pixel driver are formed in a second semiconductor die under the first semiconductor die, and the digital logic circuit is formed in a third semiconductor die under the second semiconductor die.

Image sensor device

An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

Integrated circuit devices and methods of manufacturing same

An image sensor and an electronic apparatus, the image sensor including a plurality of pixels, each pixel of the plurality of pixels including a photodiode and a transfer transistor, a reset transistor, a source-follower transistor, and a selection transistor, which correspond to the photodiode; a plurality of first interconnection lines connected to gates of the transfer transistor, the reset transistor, and the selection transistor, the plurality of first interconnection lines extending in a first direction; and a plurality of second interconnection lines connected to a source region of the selection transistor, the plurality of second interconnection lines extending in a second direction that intersects the first direction, wherein the plurality of second interconnection lines includes dummy lines on a peripheral area that is outside of a pixel area in which the pixels are located.

Image sensor with dummy lines for minimizing fixed pattern noise (FPN) and electronic apparatus including the same

Image sensors are provided including a structure capable of settling an output voltage within a very short time for implementing a high-speed image sensor. The image sensor includes a pixel area, in which a photo-diode (PD) and a transfer transistor (Tr) configured to transmit charges accumulated in the PD to a floating diffusion (FD) area are disposed; and a Tr area, which is disposed adjacent to the pixel area and includes a first Tr, a second Tr, and a third Tr, wherein a first gate oxide film disposed below a first gate electrode of the first Tr and a second gate oxide film disposed below a second gate electrode of the second Tr include channel oxide films thinner than a gate oxide film of the transfer Tr.

Image sensors having a reduced settling time

Integrated circuit devices

Integrated circuit devices including separate memory cells on separate regions of individual substrate

A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.

Semiconductor devices and methods of manufacturing the same

Some example embodiments disclose methods for selecting registered public land mobile network (RPLMN) radio access technology (RAT) modes in wireless communication devices. The method as disclosed herein includes determining location information of the wireless communication device; validating the location information; deriving a RPLMN from the validated location information when the validating is successful; storing a RPLMN access technology (AccTech) based on the derived RPLMN; and selecting a RAT mode using the stored RPLMN AccTech.

Methods for selecting radio access technology (RAT) modes in wireless communication devices

Growing community of inventors

Seongnam-si, South Korea

Jae-kyu Lee