Samsung Electronics Co., Ltd.

K. C. Tech Co., Ltd.

Jae-Kwang Choi

Bo-un Yoon

Byoung-ho Kwon

Chang-ki Hong

Si-Young Choi

Myeong-Cheol Kim

Cheol Kyu Kim

Ho-young Kim

Yong-Joon Choi

Geum-jung Seong

Hee-Don Jeong

Se-jung Park

Bo-Kyeong Kang

Ji-Eun Han

Suk-Hoon Jeong

Jong-Ho Lee

Sung-Jun Kim

Yong-Sun Ko

Kyung-Hyun Kim

Hwa-Sung Rhee

Seung-Ho Park

Kun-Tack Lee

Jae-Dong Lee

Joon-Sang Park

Sang-kyun Kim

Hyung-Suk Jung

Ji-Sung Lee

Sol Han

Hong-Jin Kim

Kwang-Bok Kim

Keon-Sik Seo

Myung-Ki Hong

Jin-Myung Hwang

Se-Rah Yun

Ki-Hwa Jung

Jun-Ha Hwang

Chang-Gil Kwon

Seung-Yeop Baek

Jae-Woo Lee

A polishing composition includes abrasive particles, a pyrrolidone containing a hydrophilic group, a dispersing agent, a first dishing inhibitor including polyacrylic acid, and a second dishing inhibitor including a non-ionic polymer.

Polishing compositions and methods of manufacturing semiconductor devices using the same

Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Semiconductor device and method for fabricating the same

A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.

Chemical mechanical polishing apparatus having pad conditioning disk and pre-conditioner unit

A polishing pad may include a base and a plurality of polishing protrusions on a surface of the base. Each polishing protrusion may include a sidewall defining an opening in a surface of the polishing protrusion opposite the base. In addition, portions of the sidewall opposite the base may define a contact surface.

Polishing pads including sidewalls and related polishing apparatuses

Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.

Dual gate stack CMOS structure with different dielectrics

Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

Method of forming self-aligned double pattern

A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.

Method for manufacturing multi-level transistor comprising forming selective epitaxial growth layer

For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.

Method and system for planarizing integrated circuit material

Growing community of inventors

Suwon-si, South Korea

Jae-Kwang Choi