Samsung Electronics Co., Ltd.

Jae-kwan Kim

Byung-kyu Lee

Du-hyun Lee

Woong Ko

Ki-yeon Yang

Joo-sun Choi

Jung-hwan Choi

Hyung-seuk Kim

An imprinting stamp and a nano-imprinting method using the imprinting stamp are provided. The imprinting stamp includes a first substrate; one or more field regions on the first substrate, the first substrate including nano-patterns; and a first dummy pattern region on the first substrate and adjacent to the field region, the dummy pattern region including first dummy patterns having greater dimensions than that of the nano-patterns, the first dummy patterns being a plurality of polygons, each of the polygons having a vertex pointing in a first direction proceeding from the field region toward the first dummy pattern region.

Imprinting stamp and nano-imprinting method using the same

A stamp includes a transparent body having an inner chamber containing an inlet/outlet tube configured to have a fluid injected and removed therefrom.

Stamp, method of fabricating the stamp, and imprint method using the same

A template system, and a nano-imprint method using the same, include a template having a nano-pattern and configured to transfer the nano-pattern to a resin material on a substrate, and a pressure controlling apparatus configured to change a pressure of the template with respect to the substrate according to an intensity of bubbles captured between the substrate and the template.

Template system and nano-imprint method using the same

A stamp includes at least one protrusion on a protrusion pattern, and an end portion of the at least one protrusion may have a non-planarized surface. The end portion of the protrusion may have a concave structure, that is, the end portion includes a center region and an edge region, and the edge region is higher than the center region.

Stamp, method of manufacturing the same, and imprinting method using the stamp

A semiconductor device for detecting and compensating for a propagation delay of a tri-state bidirectional bus connected between a master block and a plurality of slave blocks. The master block controls the slave blocks. A bidirectional bus connects the master block and each of the slave blocks and accommodates transmission of data therebetween. A unidirectional bus is connected between the master block and each of the slave blocks. The unidirectional bus accommodates the transmission of control signals generated in the master block to the slave blocks wherein the master block detects a propagation delay time between the master block and the slave blocks. The master block counts the number of clocks from a time when a selected slave block transmits an allocated symbol to a time when the allocated symbol reaches the master block such that a propagation delay time between the master block and the selected slave block is detected and stored.

Method of compensating for propagation delay of tri-state bidirectional bus in a semiconductor device

Example embodiments are directed to an apparatus and method for measuring a pulse width. A side-band signal generator may be configured to receive a given data pattern and output a side-band signal by modulating a pulse width of the received data pattern in a test mode. A phase detector may be configured to receive the side-band signal and a reference clock signal, and output a pulse signal corresponding to a phase difference between the received side-band signal and the reference clock signal. A charge pump may be configured to receive the pulse signal and output an output voltage by increasing or decreasing the output voltage based on the pulse signal. A pulse width measurer may be configured to receive the output voltage of the charge pump and determine whether pulses forming the side-band signal have appropriate widths based on whether the output voltage is included in a desired reference voltage range.

Method and apparatus for measuring pulse widths of a side-band signal

A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic impedance of a metal line connected to an external circuit, pre-emphasizes at least one input signal, and includes a control circuit and an output circuit. The control circuit matches the output impedance of the dynamic output circuit to the characteristic impedance of the metal line in response to at least one output signal, and outputs a plurality of resistor control signals which are used to pre-emphasize at least one input signal in response to the input signal. The output circuit controls the output impedance and pre-emphasizes the input signal in response to the resistor control signals, and outputs the output signal.

Dynamic output buffer circuit

A semiconductor memory device for compensating latency by stacking reference data. The semiconductor memory device compensates the latency and test errors between two signals by detecting the latency of the two signals and stacking the reference data without using an extra signal. Accordingly, a system can be simplified and power consumption can be reduced when testing the semiconductor memory device, since the extra circuit is unnecessary to synchronize a data sync signal with output data.

Semiconductor memory device and method for stacking reference data

A data transmission circuit includes a control signal generation circuit, a write state machine, a conversion circuit, a read state machine, and a selection circuit. The control signal generation circuit receives a strobe signal and a clock signal in response to an enable signal, generates a write control signal that is activated in response to a rising edge of the strobe signal, and generates a read control signal that is activated in response to a first rising or falling edge of the clock signal after the write control signal is activated. The write state machine is activated in response to the write control signal, changes its internal state in synchronization with the strobe signal, and sequentially outputs input control signals in response to the changed internal state. The conversion circuit converts serial data to parallel data in response to the input control signal sequentially output from the write state machine and latches the parallel data. The read state machine is activated in response to the read control signal, changes its internal state in synchronization with the clock signal, and sequentially outputs output control signals in response to the changed internal state. The selection circuit outputs the parallel data latched in the conversion circuit in the same order that the serial data is sequentially input to the conversion circuit in response to the output control signals sequentially output from the read state machine.

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Daejeon, South Korea

Jae-kwan Kim