Hyundai Electronics Industries Co. Ltd.

Jae-Kap Kim

In-Sool Chung

Kwang-Soo Kim

A semiconductor device and a method of fabricating the same are disclosed. A resistor, a lower plate of an analog capacitor and a gate electrode of a MOS transistor are simultaneously formed over a substrate where an isolation film is formed. Junction region are formed at both sides of the gate in the substrate. A dummy gate electrode over the resistor where a first insulating layer is arranged between the resistor and the dummy gate electrode and an upper plate over the lower plate where a second insulating layer is arranged between the lower and upper plates, are simultaneously formed. A metal silicide layer is then formed over the dummy gate electrode, the resistor, the gate electrode, the junction regions and the lower and upper plates of the analog capacitor.

Semiconductor device

The present invention discloses a static random access memory cell having a reduced cell size and method of manufacturing the same. According to the invention, the SRAM cell includes: a word line and a bit line; an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line; a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to the data inputted from the access device; and a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to the data inputted from the access devices.

Method of manufacturing SRAM cell

An SRAM cell and a method of manufacturing the same are disclosed. An SRAM cell including pull down devices, access devices and pull up devices each having source and drain regions with LDD structure, the source and drain regions of the access devices having: N,source and drain regions; N,source and drain regions formed under the N,source and drain regions; and P,impurity regions whose predetermined portion is overlapped with the N,source and drain region.

Method of manufacturing SRAM having enhanced cell ratio

SRAM cell

An SRAM cell capable of enhancing the cell ratio and method of manufacturing the same are disclosed. The SRAM cell has pull-up devices, pull-down devices and access devices that interconnected at cell nodes, including: current reduction part for reducing current of the access devices, wherein the current reduction part is connected with the access devices and the cell nodes.

The present invention introduces an SRAM cell which enhances immunity to soft errors and a manufacturing method thereof. A method of manufacturing an SRAM cell having access devices, pull-up devices and pull-down devices and forming a cell node junction in common junction regions of the pull-down devices and the access devices, the manufacturing method including the steps of: providing a semiconductor substrate of which active regions are difined and gate insulating layers and gates are formed on thereof; forming N.sup.- junction regions in the substrates of both sides of the gates for the pull-down devices region and the access devices region, wherein the N.sup.- junction regions formed in the cell node are separated therein and are adjacent to the gates thereof; forming the insulating layer spacers on both side-walls of the gates; and forming N.sup.+ junction regions in the substrate of both side of the spacers for the pull-down devices region and the access devices region.

Disclosed is a semiconductor device having an enhanced current amount ratio, and a manufacturing method thereof. The semiconductor device includes a first transistor and a second transistor. There is a selective electric current capacity difference between the first transistor and the second transistor, wherein a gate degeneracy of the first transistor is different from a gate degeneracy of the second transistor. Among the first and second transistors, the gate degeneracy of the transistor requiring a small amount of current is higher than the gate degeneracy of the transistor requiring a large amount of current.

Method for manufacturing a static random access memory cell

Disclosed is a manufacturing method of semiconductor device which can simplify the manufacturing procedures for transistors with different gate insulation film thickness in the same substrate. According to the present invention, a manufacturing method for semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other, is formed by the following processes. First, a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films, is provided. Next, a N well is formed in the low and high voltage PMOS transistor regions and threshold voltage adjustment ions for high voltage PMOS transistor are then implanted into the N well. Afterward, a P well is formed in the low and high voltage NMOS transistor regions and threshold voltage adjustment ions for low voltage NMOS transistor are then implanted into the P well. Next, a mask pattern exposing the high voltage NMOS transistor region and the low voltage PMOS transistor region is formed on the substrate. Threshold voltage adjustment ions for low voltage PMOS transistor are implanted into the exposed P well of the high voltage NMOS transistor region and the N well of the low voltage PMOS transistor region and the mask pattern is then removed. Next, a first gate insulation film is formed on the substrate and the first gate insulation film existing on the low voltage NMOS and PMOS transistors regions is removed. A second gate insulation film is then formed on the substrate.

Method of manufacturing a semiconductor device including implanting

Method of fabricating semiconductor device

The present invention discloses a semiconductor device having a triple well structure. The semiconductor device includes a N-type impurity doped buried layer, formed in the semiconductor substrate at a predetermined depth from the surface of the first active region; a first P-type well region formed beneath the second active region which is adjacent to the first active region; a second P-type well region formed in the semiconductor substrate to a depth from the surface of the first active region; a first N-type well region formed beneath the third active region; a second N-type well region formed beneath selected portion of the isolation film defining first active region and the second active region; and a first P-type doping region and a second N-type doping region formed respectively right beneath the surface of the first active region and right beneath the surface of the second active region, wherein the dopant concentration of the first doping region is lower than that of the second doping region.

Method of fabricating a semiconductor device having triple well structure

Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the water, is formed on an overall surface of the substrate. A first interconnection layer is electrically connected with the first impurity diffusion region through the first contact hole, and a second interconnection layer is electrically connected with the second impurity diffusion region and the predetermined portion of the wafer through the second contact hole.

Semiconductor device having a SOI structure and a manufacturing method

The present invention to provide a method of manufacturing an analog semiconductor device capable of minimizing the CD variation of a gate and improving the integration of a semiconductor device. First, a semiconductor substrate in which isolation films are formed is provided. A gate insulating layer, a first conductive layer, a dielectric layer and a second conductive layer are then formed on the substrate in sequence. Next, a first photoresist pattern is formed on the predetermined portion of the second conductive layer. The second conductive layer and the dielectric layer are then patterned using the first pattern as an etch mask, to form a first pattern for gate electrode on the substrate between the isolation films and form a second pattern for a lower capacitor electrode on the predetermined portion of the isolation film. Next, the first photoresist pattern is removed and a second photoresist pattern for an upper capacitor electrode is then formed on the second pattern. The second conductive layer of the first and second patterns and the exposed first conductive layer at both sides of the first and second patterns are etched using the dielectric layer, the gate insulating layer and the isolation films as an etch stopper and then the second photoresist pattern is removed.

Method of manufacturing analog semiconductor device

Disclosed is a method of manufacturing a complementary metal-oxide semiconductor device. The method includes the steps of: forming a plurality of field oxide layers; forming a screen oxide film on each surface of the first, second, third and fourth active regions; forming a first mask pattern for exposing first and second active regions; forming a N-type well to a selected depth from each surface of the exposed first and second active regions; forming a N-type ion implanted layer right beneath each surface of the first and second active regions; removing the first mask pattern; forming a second mask pattern for exposing the third active region; forming a P-type well to a selected depth from the surface of the exposed third active region; forming a first P-type ion implanted layer right beneath the surface of the third active region; removing the second mask pattern; forming a third mask pattern for exposing first and fourth active regions; forming a second P-type ion implanted layer for controlling a third threshold voltage right beneath each surface of the first and fourth active regions; and forming a gate electrode including a gate oxide film on the first, second, third and fourth active regions.

Method of manufacturing a complementary metal-oxide semiconductor device

An SRAM cell capable of enhancing the cell ratio and method of manufacturing the same are disclosed. The SRAM cell has pull-up devices, pull-down devices and access devices that interconnected at cell nodes, including : current reduction part for reducing current of the access devices, wherein the current reduction part is connected with the access devices and the cell nodes.

Growing community of inventors

Kyoungki-do, South Korea

Jae-Kap Kim