Hyundai Electronics Industries Co. Ltd.

Dongbu Electronics, Co. Ltd.

Jae Kap Kim

In S Chung

Chul G Ko

Jin Soo Han

Wi Sik Min

Gon Son

Ei Sam Jeong

The present invention discloses a dynamic random access memory and the method for fabricating thereof. A first silicon substrate having a trench capacitor and a second silicon substrate having a transistor are formed with a double layer, which is interposed an insulation layer between therewith, thereby forming a trench capacitor at a region, which is used to be formed a transistor in the conventional art. Accordingly, when forming the trench capacitors, in which the numbers are the same as the conventional art, at the same silicon substrate area, a trench capacitor with large in diameter and shallow in depth can be formed, thereby performing a trench capacitor forming process. According to the present invention, after forming a trench, successive processes become easy and reliability of device can be enhanced.

Dynamic random access memory and the method for fabricating thereof

The disclosed semiconductor device includes a semiconductor substrate, a logic circuit area formed on the semiconductor substrate, the logic circuit area includes transistors for driving bit lines, and a ferroelectrics memory area laminated on the logic circuit area and including a transistor area and a capacitor area. Also the disclosed method of fabricating the semiconductor device includes the steps of forming a logic circuit area on a semiconductor substrate, the logic circuit area includes interconnection wirings connected to transistors for driving bit lines, forming bit lines electrically connected to the interconnection wirings at the upper side thereof, forming a silicon film connected to the bit lines at the upper side thereof and defining a cell forming area, forming transistors on the silicon film, each transistor including a gate electrode, a source electrode, and a drain electrode, and forming capacitors electrically connected to the source electrodes at the upper side of the transistor.

Semiconductor device and method of manufacturing thereof

An method for fabricating a semiconductor device reduces a size of a MOSFET by self aligning a gate electrode with a device isolation insulation film. Thus, the gate electrode is not overlapped with the device isolation insulation film, differently from a conventional method for forming a MOSFET by partially overlapping the gate electrode with the device isolation insulation film in consideration of misalignment and CD variations in a mask process. As a result, a size of the MOSFET is reduced, thereby efficiently achieving the high integration of the semiconductor device.

Method for fabricating semiconductor device including self aligned gate

Method for fabricating semiconductor device

Disclosed is a method of manufacturing a mask for conductive wirings in a semiconductor device, wherein the conductive wirings are formed on a semiconductor substrate of the semiconductor device, comprising the steps of: (a) calculating data for the entire regions of the semiconductor substrate on which the conductive wirings are formed; (b) reading the size, shape and position of the conductive wiring patterns for the conductive wirings to generate data for conductive wirings, and storing the generated conductive wirings data; (c) extending the conductive wirings data by a predetermined size to generate data for the extended conductive wirings; (d) subtracting the extended conductive wirings data from the data for the entire regions of the semiconductor substrate to calculate a differential data between the extended conductive wirings data and the entire regions data, and to generate data for dummy conductive wiring pattern; (e) adding the conductive wirings data to the dummy conductive wiring pattern data to form a pattern the size and position of which correspond to data obtained by the addition operation on the mask by using a clear field method.

Method of manufacturing mask for conductive wirings in semiconductor device

Disclosed is a method for fabricating a semiconductor device including stacked capacitors on a semiconductor substrate having a logic circuit region formed with a circuit and a RAM cell region formed with a plurality of transistors, involving the steps of forming an insulating film to a thickness corresponding to a height of stacked capacitors, to be formed, over an upper surface of the semiconductor substrate, partially removing the insulating film from the RAM cell region, thereby forming a space in which the stacked capacitors are to be formed, forming the stacked capacitors in the space, and partially removing the insulating film from the logic circuit region, and forming interconnection lines for the logic circuit in a space defined in the logic circuit region by virtue of the removal of the insulating film. In accordance with this method, steps formed during the formation of capacitors are removed prior to subsequent processing steps for forming layers over those capacitors. Accordingly, it is possible to accurately pattern the layers formed after the formation of the capacitors. It is also possible to achieve a desired fineness of interconnection lines.

Method for fabricating semiconductor device including stacked capacitors

Disclosed is a method for fabricating a semiconductor device including stacked capacitors, in which dummy plate electrodes and charge storage electrodes are formed at a region other than a memory cell region, to control a topology resulting from capacitors, thereby allowing fine interconnection lines to be formed after the formation of those capacitors. In accordance with this method, dummy plate electrodes and charge storage electrodes, each of which has the same height as that of the stacked capacitor, are formed at the logic circuit region when the stacked capacitor are formed at the memory cell region.

The disclosed semiconductor device comprises a semiconductor substrate, a logic circuit area formed on the semiconductor substrate, the logic circuit area includes transistors for driving bit lines, and a ferroelectrics memory area laminated on the logic circuit area and including a transistor area and a capacitor area. Also the disclosed method of fabricating the semiconductor device comprises the steps of forming a logic circuit area on a semiconductor substrate, the logic circuit area includes interconnection wirings connected to transistors for driving bit lines, forming bit lines electrically connected to the interconnection wirings at the upper side thereof, forming a silicon film connected to the bit lines at the upper side thereof and defining a cell forming area, forming transistors on the silicon film, each transistor including a gate electrode, a source electrode, and a drain electrode, and forming capacitors electrically connected to the source electrodes at the upper side of the transistor.

Ferroelectric memory integrated circuit

A method for fabricating a semiconductor memory device. The method includes providing a semiconductor substrate where a transistor has been formed; forming a bit line electrically connected to a second contact plug on a drain region and forming a contact hole exposing a first contact plug on a source region; forming an etch barrier film having a uniform thickness at the inner walls of the contact hole and on the bit line; forming an interlayer insulation film; forming a storage electrode contact by etching the interlayer insulation film and the etch barrier film on the first contact plug; forming a third contact plug electrically connected to the first contact plug in the storage electrode contact; and forming on the third contact plug a capacitor having a stacked structure of a storage electrode, and a dielectric film and a plate electrode surrounding the storage electrode.

Method for forming memory cell of semiconductor memory device

A method for fabricating NOR type memory cells of a nonvolatile memory device, floating gate insulating film, a floating gate electrode, a control gate insulating film, a control gate electrode, and an insulating film sequentially stacked in the shape of pattern on each of memory cell regions of a semiconductor substrate defined by an isolation film are formed; a source electrode and a drain electrode are formed in portions of the semiconductor substrate exposed at both sides of the gate electrode, a first etching barrier film is formed on the resultant; a first interlayer insulating film is formed on the first etching barrier film in a planarized fashion; a desired portion of the first interlayer insulating film is etched to form a first contact hole exposing the source and drain electrodes; a first conductive film in a planarized fashion is formed on the resultant to bury the first contact hole; the first conductive film is etched to form a source electrode line contacting the source electrode and a contact plug contacting the drain electrode; a second etching barrier film is formed on the resultant; a second interlayer insulating film is formed in a planarized fashion on the second etching barrier film; a desired portion of the second insulating film is etched to form second contact hole exposing the contact plug; and a bit line connected to the contact plug is formed via the second contact hole on the second interlayer insulating film.

Method for fabricating NOR type memory cells of nonvolatile memory device

Provided is a method of manufacturing a semiconductor device having a stacked capacitor configured to reduce a step difference between a memory cell region and a logic circuit region adjacent thereto. In the method of manufacturing a semiconductor device, a sacrificial film removed after formation of the semiconductor device having a stacked capacitor, is preserved in the logic circuit region to be used as an interlayer insulating film. Thus, a step difference between a memory cell region having the capacitor and a logic circuit region, is removed, thereby facilitating formation of multi-layered interconnection wirings formed after forming the capacitor, and attaining fineness of the interconnection wirings.

Method of manufacturing semiconductor device

In DRAM comprising a read pass transistor, a write pass transistor and a storage transistor, a depletion transistor is connected to a source of the storage transistor. On a part of the source and drain of the depletion transistor, by forming an impurity region of same conductivity as that of the substrate on which the transistors are formed, a substrate voltage applied to the substrate is supplied to the storage transistor through the depletion transistor. An additional metal wire for connecting the source of the storage transistor to Vss voltage (ground voltage or substrate voltage) terminal and a contact hole area for such metal wire are not required. Accordingly, a high integration of the semiconductor can be accomplished and a reduction of reliability thereof can be decreased.

Semiconductor memory device

A semiconductor device comprising a dual polysilicon gate structure in which the P type polysilicon gate is connected with the N type polysilicon gate by a bilayer conductive wiring structure without any contact, thereby significantly contributing to high integration, and a method for fabricating the semiconductor device such that the production yield is improved.

Semiconductor device and method for fabricating the same

A ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of word lines extending in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an M&times;N array while being connected to associated ones of the lines. The unit cells are grouped into a plurality of unit cell groups. A dummy cell group comprises a plurality of dummy cells that are connected to an associated one of the bit lines of an optional position on the associated bit line. A first switching transistor group comprises a plurality of switching transistors that serve to switch a connection among associated ones of the unit cells on one of the bit lines corresponding to an associated one of the dummy cells in response to a control signal externally applied thereto, and a second switching transistor group comprises a plurality of switching transistors that serve to erase data stored in an associated one of the dummy cells in response to a control signal externally applied thereto. Respective capacitors of the dummy cells are made of a dielectric film having no spontaneous polarization characteristic.

Growing community of inventors

Kyoungki-do, South Korea

Jae Kap Kim