Skhynix Inc.

Hynix Semiconductor Inc.

Jae Jung Lee

Ki Hong Lee

Wan Sup Shin

Young Geun Jang

A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.

Semiconductor device and manufacturing method of the semiconductor device

A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalk of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.

A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.

A semiconductor memory device of the present invention includes a first dielectric layer located on an upper surface of a semiconductor substrate including contact area and a non-contact area, an etching stop layer pattern formed to expose the first dielectric layer in the non-contact area and cover the first dielectric layer in the contact area, a contact hole extended to the semiconductor substrate of the contact area through the etching stop layer pattern and the first dielectric layer, a contact plug located in the contact hole, and a conductive line connected to the contact plug.

Semiconductor memory device, memory system including the same and method of manufacturing the same

A flash memory device and method of fabricating thereof. In accordance with the method of the invention, a tunnel dielectric layer and an amorphous first conductive layer are formed over a semiconductor substrate. An annealing process to change the amorphous first conductive layer to a crystallized first conductive layer is performed. A second conductive layer is formed on the crystallized first conductive layer. A first etch process to pattern the second conductive layer is performed. A second etch process to remove an oxide layer on the crystallized first conductive layer is performed. A third etch process to pattern the amorphous first conductive layer is performed.

Flash memory device and method of fabricating the same

A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor substrate in the peripheral region. An insulating layer is formed over the gate dielectric layer. An isolation trench is formed in the peripheral region, the isolation trench defining first and second trenches having different opening widths. A first gap-fill layer is provided over the isolation trench and on the step. The first gap-fill layer has a first portion on a sidewall of the insulating layer, a second portion on a sidewall of the gate dielectric layer, and a third portion at least partly filling the second trench of the isolation trench, the second portion being thicker than the first portion. A wet etch is performed to remove at least part of the first gap-fill layer. A second gap-fill layer is provided over the first gap-fill layer in the isolation trench to form an isolation structure. The second portion of the first gap-fill layer is configured to protect the gate dielectric layer during the wet etch step.

Method of forming isolation structure of flash memory device

Provided is a method for forming a metal line in a semiconductor device. The method forms round portions at top edges of an insulation film by means of a polymer and then etches the rest portion (i.e., sidewall parts) in an almost vertical direction, which makes it possible to shrink down a width of a patterned insulation film at maximum nevertheless of a dimension of a metal-line patterning mask. By way the method, an interval between adjacent metal lines is extended at maximum, preventing mutual interference between the metal lines.

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Seoul, South Korea

Jae Jung Lee