Samsung Electronics Co., Ltd.

Postech Research and Business Development Foundation

Daegu Gyeongbuk Institute of Science and Technology

Jae-Joon Kim

Hyungjun Kim

Sungju Ryu

Jinseok Kim

Yulhwa Kim

Taesu Kim

Youngtaek Oh

Junki Park

Jaeha Kung

A method for processing data based on a neural network including a first layer including axons and a second layer including neurons, includes receiving synaptic weights between the first layer and the second layer; generating presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, from the synaptic weights; and storing the presynaptic weights and the postsynaptic weights in a synapse memory.

Neuromorphic processor and operating method thereof

Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature 5 bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number 10 of digits of the addition result depending on a shift value to generate a shifted addition result and an accumulator generating output feature data based on the shifted addition result.

Neural network accelerator

Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Electronic device for configuring neural network

A matrix data processing method performed by a computing device which performs a matrix multiplication operation includes, with respect to each of one or more elements included in a matrix, when a value of each element satisfies a designated condition, determining the element to be a don't-care element and determining an output value of the don't-care element, generating a bitstream based on the output value of the don't-care element and index values of valid elements included in the matrix, and equally dividing the bitstream into pieces of a designated number, and generating a Huffman code corresponding to each of a plurality of lower bitstreams that are generated as a result of the equal division.

Method and apparatus for processing matrix data through relaxed pruning

Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.

Growing community of inventors

Pohang-si, South Korea

Jae-Joon Kim