International Business Machines Corporation

Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Skhynix Inc.

Postech Research and Business Development Foundation

Purdue Research Foundation

Jae-Joon Kim

Ching-Te Kent Chuang

Rahul M Rao

Keunwoo Kim

Hyungjun Kim

Aditya Bansal

Yu-Shiang Lin

Jinseok Kim

Yulhwa Kim

Rajiv V Joshi

Keith Aelwyn Jenkins

Joel Abraham Silberman

Kaushik Roy

Liang-Teck Pang

Saibal Mukhopadhyay

Taesu Kim

Insup Shin

Shih-Hsien Lo

Junki Park

Stephen Victor Kosonocky

Barry P Linder

Sungho Kim

Sam Gat-Shang Chu

Manjul Bhushan

Kai Zhao

Saiful Islam

Pong-Fei Lu

Youngjae Jin

Sungju Ryu

Amlan Ghosh

Eunhwan Kim

Eun Hwan Kim

Euiseok Kim

Ching Te Chuang

Tae-Hyoung Kim

Shao-yi Wang

Hyung-il Kim

Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Electronic device for configuring neural network

Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Artificial neural network circuit

An operating method of a neuromorphic processor which processes data based on a neural network including a first layer including axons and a second layer including neurons includes receiving synaptic weights between the first layer and the second layer, decomposing the synaptic weights into presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, and storing the presynaptic weights and the postsynaptic weights. A precision of each of the synaptic weights is a first number of bits, a precision of each of the presynaptic weights is a second number of bits, and a precision of each of the postsynaptic weights is a third number of bits. The third number of the bits is smaller than the first number of the bits.

Neuromorphic processor and operating method thereof

A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.

Dividing neural networks

A method formats a weight matrix in a current layer included in a neural network. The method includes calculating a row length for each row of the weight matrix based on a number of elements each of which has non-zero value; storing rearrangement information including result of sorting rows in the order of row lengths; performing a row transformation or the row transformation and a column transformation on the weight matrix using the rearrangement information; distributing rows of a transformed weight matrix to a plurality of processing elements (PEs); and generating formatted data including one or more group data each including values and column information being processed in each of the PEs.

Method for formatting a weight matrix, accelerator using the formatted weight matrix, and system including the accelerator

Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

Neural network accelerator

A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.

Neuromorphic system and operating method thereof

A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.

Pseudo-complementary logic network

A method for formatting a weight matrix including a plurality of sub matrices each being multiplied with an input vector may include sequentially adding weight information included in respective first columns of the plurality of sub matrices to formatted data; and sequentially adding weight information included in respective second columns of the plurality of sub matrices to the formatted data after the weight information from the first columns of the plurality of sub matrices. The weight information may be non-zero weight information.

Method of formatting a weight matrix, an accelerator using the formatted weight matrix, and a system including the accelerator

Provided are a weight matrix circuit and a weight matrix input circuit. The weight matrix circuit includes a memory array including n input lines, m output lines, and n&#xd7;m resistive memory devices each connected to the n input lines and the m output lines and each having a non-linear current-voltage characteristic, an input circuit connected to each of the input lines, and an output circuit connected to each of the output lines. The input circuit is connected to the resistive memory devices such that the weight matrix circuit has a linear current-voltage characteristic.

Weight matrix circuit and weight matrix input circuit

Provided are a true random number generator and an oscillator. The random number generator includes an oscillator configured to output signals and oscillate a random number of times until phases of the signals being output are inverted with respect to each other after initialization, and a counter configured to count the number of oscillations. The counted number of oscillations is used as a seed for generating a random number.

True random number generator and oscillator

Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

Pulsed-latch based razor with 1-cycle error recovery scheme

Growing community of inventors

Yorktown Heights, NY, United States of America

Jae-Joon Kim