Samsung Electronics Co., Ltd.

Industry-university Cooperation Foundation Sogang University

Jae-Jin Shin

Kyung-Hyun Kim

Ji-Hoon Choi

Jin-Gyun Kim

Jae-Jik Baek

Ju-Yong Lee

Yoo-Chul Kong

Gon-jun Kim

Sung-Hyuk Byun

Jin-Woo Yang

Dan-keun Sung

Jeong-Won Heo

Sung-gil Kang

Min-seop Park

In-hye Jeong

Kyung-geun Lee

Jung-ho Kim

Jae-Hwang Sim

Tae-Hyun Kim

Jung-Ho Kim

Seung-Pil Chung

Jung-Geun Jee

Jin-Kyu Lee

Hee-Woo Rhee

Jong-Heun Lim

Sang-Ryol Yang

Su-Kyung Kim

Kook Heon Char

Sang-ryol Yang

Bongjin Moon

Sung-Kyu Min

Sung-Kwon Park

Choong-Kee Seong

Do Young Yoon

Kyung-Geun Lee

Jung-Hun No

Se Jung Park

Hyun-Min Park

Hong-Ik Kim

Tae-Woong Kim

Joon-Soon Im

A substrate processing apparatus includes a processing chamber; a susceptor provided in the processing chamber, wherein the susceptor is configured to support a substrate; a first plasma generator disposed on one side of the processing chamber; and a second plasma generator disposed on another side of the processing chamber, wherein the second plasma generator is configured to generate plasma by simultaneously supplying a sinusoidal wave signal and a non-sinusoidal wave signal to the susceptor. By using a substrate processing apparatus, a signal source device, and a method of processing a material layer according to the inventive concept, a smooth etched surface may be obtained for a crystalline material layer without a risk of device damage by RDC.

Substrate processing apparatus, signal source device, method of processing material layer, and method of fabricating semiconductor device

A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

Non-volatile memory device and method of manufacturing the same

Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

Three dimensional semiconductor memory device and method of fabricating the same

A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.

Methods of manufacturing semiconductor devices

A channel-switching apparatus and method in a digital broadcasting system omits conditional access control in logical channel-switching in one physical channel from processes that are executed for channel-switching in a digital broadcasting system, thereby reducing channel-switching time.

Channel switching in a digital broadcasting system

A method for providing pay-per-view service while observing an OpenCable standard in realization of bi-directional digital cable broadcasting includes a method for interfacing between a set-top box and a point of deployment (POD), the method comprising the steps of: receiving, at the set-top box, an arbitrary program event purchase-related instruction inputted by a user, generating an object based on the arbitrary program event purchase-related instruction, and transmitting the arbitrary program event purchase-related instruction object to the POD; and receiving, at the POD, the object transmitted by the set-top box, generating an answer object based on the reception, and transmitting the answer object to the set-top box.

Apparatus and method for interfacing between set-top box and point of deployment for pay-per-view service

This invention is related to a reactive nanoparticular cyclodextrin derivative useful as a porogen and a low dielectric matrix, with excellent mechanical properties and uniformly distributed nanopores, manufactured by sol-gel reaction of the above reactive cyclodextrin. Furthermore, this invention also is related to an ultralow dielectric film, with uniformly distributed nanopores, a relatively high porosity of 51%, and a relatively low dielectric constant of 1.6, manufactured by thin-filming of the conventional organic or inorganic silicate precursor by using the above reactive nanoparticular cyclodextrin derivative as a porogen.

Reactive cyclodextrin derivatives as pore-forming templates, and low dielectric materials prepared by using the same

An ATM switch having the buffer threshold controller to control the cell input into the switching element using the back-pressure signal and a method for determining the buffer threshold according to the buffer threshold controller are disclosed. The ATM switch includes buffer pool storing the cell input to the switch; buffer pool control part storing the buffer pool occupancy information per input port of the buffer pool; threshold control part receiving the buffer pool occupancy information from the buffer pool control part and calculating the threshold per input port periodically and then sending it to the buffer pool control part; input crosspoint control part controlling the cells input to the buffer pool by receiving the control signal from the buffer pool control part; and output crosspoint control part controlling the cells output from the buffer pool by receiving the control signal from the buffer pool control part. The method includes the steps of calculating r , the buffer pool occupancy rate of the ith input port (i&equals;1, 2, 3, . . . , N); calculating r , the threshold of the buffer pool occupancy rate of the ith input port; calculating L , the number of occupation of the cells in the buffer pool of the ith input port; calculating the difference, D &equals;t &minus;L (k&equals;1, 2, 3, N . . . , N) between t , the threshold of the jth input port and L , the number of cells stored in the buffer pool, where i&ne;j (j&equals;1, 2, 3, . . . , N); calculating t , the threshold in case where the t &minus;L is the kth value in descending order from the N input ports; calculating b , minimum threshold to guarantee the minimum cell input; and comparing &Dgr;, the minimum unit of increase or decrease of the threshold and the value of t &minus;b .

ATM switch and a method for determining buffer threshold

A controller for the logical buffer depth in ATM switching system and a method for determining the logical queue depth, using the back-pressure signal and the occupied buffer depth information and supporting the P classes, are disclosed. The controller includes Routing Table Element making tag for routing of input cell; Input Buffer storing the cell that a tag is attached to in said routing table element; Switch fabric that reads the cell from said input buffer and then switches it to the output port; and Input buffer controller controlling the logical queue size in said input buffer. And the method for determining the logical queue depth includes the steps of calculating the back-pressure signal occurrence rate b,of the ith class; calculating the back-pressure signal occurrence threshold rate b,of the ith class; calculating the buffer depth T,of the logical queue of the ith class; calculating threshold values T,T,of the two buffer depths of the ith class; calculating the buffer size L,of the logical queue of the ith class; calculating the empty area size D,(j&equals;1, 2, 3, L, P) of logical queues for the number of p classes.

Input buffer controller using back-pressure signals in ATM switches and a method for determining the logical queue size

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Seoul, South Korea

Jae-Jin Shin