Samsung Electronics Co., Ltd.

Korea University Research and Business Foundation

Jae-Jin Park

Ji-hyun Kim

Seung-Hoon Lee

Dong-Hyuk Lim

Woo-seok Kim

Tae-Kwang Jang

Dae-Young Chung

Ji-Hwan Hyun

Do-Hyung Kim

Sung-Jin Kim

Hee-Seok Lee

Dong-Seok Lee

Jin-Ho Seo

Min-Young Song

Chul-Woo Kim

Dong-Uk Park

Jae-Youl Lee

Sang-Kyu Kim

Eun-seok Shin

Seung-Bin You

Young-Ho Kwak

Kang-Yeop Choo

Se-ra An

Min-young Kang

Wang Gun Yu

Kun-Yong Yoon

Jong-Phil Hong

A lock-in amplifier includes a clock signal generator configured to generate a first demodulation clock signal and a second demodulation clock signal having a phase difference of 90 degrees and a same demodulation frequency; and a detector configured to, based on an input signal, the first demodulation clock signal, and the second demodulation clock signal, provide an offset voltage corresponding to an offset of the lock-in amplifier in a first operation mode, and provide a first output voltage and a second output voltage, each of which correspond to a demodulation frequency component of the input signal in a second operation mode.

Lock-in amplifier, integrated circuit and portable measurement device including the same

A resonator oscillator that may be included in a gas sensing system may include an oscillator that may be electrically connected to an external resonator through a conductive line. The oscillator may generate an oscillating signal having a frequency corresponding to a resonance frequency of the external resonator in an oscillating path. A spurious resonance removal circuit on the oscillating path may remove spurious resonance caused by the conductive line from the oscillating path. A gas sensing system may include the oscillator, a resonator that includes a sensor configured to sense a gas, and a frequency counting logic that receives the oscillating signal and a reference clock signal, performs a counting operation on the oscillating signal according to a logic state of the reference clock signal to generate a counted value, and generate a gas sensing output indicating a sensed gas based on the counted value.

Film bulk acoustic resonator oscillators and gas sensing systems using the same

An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

Edge detectors and systems of analyzing signal characteristics including the same

An integrated circuit includes an operational circuit and a test circuit for measuring a leakage current associated with all or part of the operational circuit. The leakage current measurement circuit may include a mirror circuit configured to mirror leakage current to a current-to-voltage converter and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value.

Circuit of measuring leakage current in a semiconductor integrated circuit

A system-on-chip includes a body bias voltage generator having a voltage divider and a filter. The voltage divider includes a switched capacitor circuit and a resistor circuit. The switched capacitor circuit operates based on a first clock signal and a second clock signal. The resistor circuit outputs a first voltage through a first node, which is coupled to the switched capacitor circuit and the resistor circuit. The first and second clock signals have a same frequency. The filter performs a filtering operation on the first voltage to generate a body bias voltage.

System-on-chip including body bias voltage generator

A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell.

Delay cell, delay locked look circuit, and phase locked loop circuit

A temperature controlled oscillator includes an oscillation unit and a filter unit. The oscillation unit is configured to generate at least one reference voltage based on a supply voltage and a ground voltage, and to generate an oscillation signal having a period varying according to a temperature, the oscillation unit configured to generate the oscillation signal based on a filter voltage and the at least one reference voltage. The filter unit is configured to generate the filter voltage based on the oscillation signal.

Temperature controlled oscillator and temperature sensor including the same

A semiconductor package includes a package substrate; an integrated circuit chip formed on one surface of the package substrate; and a sealed quartz oscillator formed on at least one of an inside, one surface, and the other surface of the package substrate, wherein the sealed quartz oscillator includes a substrate, a quartz blank formed on one surface of the substrate, and a sealing cap covering at least one surface of the quartz blank and including metal.

Sealed crystal oscillator and semiconductor package including the same

A semiconductor IC including a supply voltage generator, one or more first circuit blocks, and one or more second circuit blocks. The supply voltage generator is configured to generate a first supply voltage and a second supply voltage based on an external supply voltage, and to provide the first supply voltage to a first power bus and the second supply voltage to a second power bus. The first circuit blocks are connected between the first power bus and the second power bus, and the second circuit blocks are connected between the second power bus and ground.

Supply voltage generator for a display timing controller with current reuse

A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals.

Digital phase frequency detector, digital phase locked loop including the same and method of detecting phase and frequency of output signal

A phase locked loop (PLL) circuit and a system including such a PLL that may at least compensate for leakage current in a loop filter. The PLL circuit may include a voltage adjusting unit configured to pump charges based on a phase difference between an oscillation clock signal and a reference clock signal, a loop filter configured to generate a frequency control voltage, a level of which is shifted by the charge pumping of the voltage adjusting unit, a voltage controlled oscillator (VCO) configured to output the oscillation clock signal having a frequency corresponding to the frequency control voltage, and a current control circuit configured to generate a compensation current corresponding to a leakage current generated by the loop filter and allow the compensation current and the leakage current to substantially and/or completely counterbalance each other.

Phase locked loop circuit and system having the same

Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal.

Phase locked loop circuit, method of detecting lock, and system having the circuit

A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n&#x2212;1]) within the embedded clock data signal.

Display device transferring data signal with clock

A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

Clock generator to reduce long term jitter

A phase locked loop includes a phase-frequency detector and a loop filter. The phase-frequency detector compares phases of an input signal and a feedback signal to generate first and second control signals. The loop filter includes a pull-up resistor, a pull-down resistor and a capacitance unit. The loop filter receives a first reference voltage to charge the capacitance unit through a path formed by the pull-up resistor to the capacitance unit, receives a second reference voltage to discharge the capacitance unit through a path formed by the pull-down resistor to the capacitance unit and outputs a control voltage generated based on a charge amount of the charged capacitance unit. Therefore, the phase locked loop can operate at a relatively low voltage and can operate based on a control voltage with a wide input range.

Growing community of inventors

Seongnam-si, South Korea

Jae-Jin Park