Skhynix Inc.

Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Samsung Electronics Co., Ltd.

Fidelix Co., Ltd.

Hyundai Motor Company

Kia Motors Corporation

Kia Corporation

Hyundai Transys Incorporated

Jusung Engineering Co., Ltd.

Hyundai Display Technology Inc.

Daechang Seat Co.,ltd-dongtan

Hyundai Electronics Industries

Jae Jin Lee

Chang Hyun Kim

Do Yun Lee

Min Chang Kim

Hun Sam Jung

Hee Bok Kang

Jin Tae Jeong

Jin Hong Ahn

Chun Seok Jeong

Mi Hye Kim

Do Hyung Kim

Jae Koog An

Kook Jeong Seo

Kang Seol Lee

Hyung Sik Won

Sang Hyun Park

Yong Woo Lee

Sang Jin Byeon

Seung Hun Lee

Sang Hyun Lee

Seon Chae Na

Seung Hyun Kim

Ji Hoon Kim

Jae Ho Kim

Sang Min Park

Ji Eun Jang

Yong Sung Yoon

Seung Ah Joo

Chang Sik Yoo

Seok Joon Kang

Jang Woo Lee

In S Chung

Sung Cheol Kang

Seung Han Ahn

Hoe Kwon Jung

Dong Hwan Kim

Bong Su Son

Do Yun Jang

Yoon Young Kim

Chan Ki Cho

Byung Yong Choi

Kee Teok Park

In Chang Hwang

Jin Youp Cha

Seok Jun Yoon

Sang Hee Kang

Qasim Sarwar Khan

Jae Hyuk Im

Doo Bock Lee

Sang Un Choi

Min Ju Lee

Chang Seok Kang

Seok Cheol Yoon

Mi Young Kim

Ho Jin Yun

Byung Gwan Lim

Dong Hae Seo

Dong Hwan Lee

Hyun Il Kim

Myeong Ju Kwon

Chul Ho Kim

Young Woon Choi

Jong Bok Park

Wan Jun Roh

Yong Dae Jeong

Gyung Hae Aoh

Hwan Soo Shim

Jung Pil Kim

Jeong Jin

Kyoung Kl Park

A semiconductor memory device of the disclosure comprises a frequency detection circuit that detects the frequency of an input clock signal generated during a measurement time and generates a frequency confirmation data having the information on the frequency of the input clock signal; a status register that receives the frequency confirmation data and generates 1-st to m-th driving control signals; and a 1-st to an m-th operating circuit. In the semiconductor memory device of the disclosure, the operating state can be changed by detecting a frequency change of an input clock signal without an external mode register setting command. As a result, according to the semiconductor memory device of the disclosure, the time required to change the operating mode is reduced.

Semiconductor memory device for determining operation state with detecting frequency of input clock signal

An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

Aging monitoring circuit of semiconductor memory device

A data transmission/reception device comprises a data bus; a data transmission circuit that recognizes standard data, receives a transmission data, loads a code data into the data bus, and generates a flag signal; and a data reception circuit that receives the flag signal and the code data transmitted through the data bus, and recovers the code data into a reception data according to the activation of the flag signal. According to the data transmission/reception device of the disclosure, current consumption may be reduced during data transmission.

Data transmission/reception device in semiconductor system for reducing current consumption

A signal input buffer includes 1-st and 2-nd buffering blocks; a 1-st input switching block; a 2-nd input switching block; a 1-st output switching block; and a 2-nd output switching block. The signal input buffer buffers a reception signal pair and generates a buffered signal pair, and is capable of operation in a normal mode and a calibration mode, the reception signal pair includes an intrinsic reception signal and a complementary reception signal, the buffered signal pair includes an intrinsic buffered signal and a complementary buffered signal, and the calibration mode includes a 1-st calibration period and a 2-nd calibration period.

Signal input buffer for effectively calibrating offset

An analog-to-digital converter may comprise a code voltage generating part that generates a conversion code voltage according to the conversion digital code; a voltage comparing part that generates a comparison result signal by comparing the input analog voltage and the conversion code voltage; a shifting register that receives a clock signal and generates a 1-st to a n-th control pulse signals; and a code generating part that generates the conversion digital code with receiving by comparison result signal and the 1-st to the n-th control pulse signals.

Analog-to-digital converter capable of quick conversion

An input buffer circuit includes a reception sensing part that receives an input signal pair to generate an intermediate signal pair, a comparison buffering part that buffers the intermediate signal pair to generate a buffered signal pair, an intrinsic buffered signal of the buffered signal pair being controlled to a first logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, a complementary buffered signal of the buffered signal pair is controlled to a second logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, and a hysteresis control part that drives the buffered signal pair to have forward hysteresis by using at least one of the intrinsic buffered signal and the complementary buffered signal.

Input buffer circuit in semiconductor memory device having hysteresis function

An auto refresh limiting circuit includes an oscillating signal generating part that generates an internal oscillating signal, the internal oscillating signal being a pulse having a period reflecting an internal temperature of a semiconductor memory device; a masking signal generating part that generates a masking signal by using an auto refresh command signal and the internal oscillating signal, the masking signal being deactivated during a pulse of the auto refresh command signal, the pulse of the auto refresh command signal being first generated after the pulse of the internal oscillating signal is generated; and an auto refresh masking part that converts the pulse of the auto refresh command signal into a pulse of an auto refresh driving signal, the conversion of the pulse of the auto refresh driving signal being masked according to the activation of the masking signal.

Auto refresh limiting circuit for semiconductor memory device

Disclosed herein is a semiconductor memory device for reducing data read time difference between memory banks. In the semiconductor memory device of the disclosure, each of the memory banks has the delay control time controlled based on the distance from data control block or receives the signal according to the read command. Accordingly, the data read time difference is reduced in the semiconductor memory device, and the operation time margin of the data control block is improved.

Semiconductor memory device for reducing data read time difference between memory banks

In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

Image synchronization device and image information generation apparatus including the same

A combination structure of a seat frame includes: a first and a second side cushion frames installed on a first and a second sides of a seat, and configured to slide forward and rearward, wherein the first and the second sides of the seat are opposite to each other; a center cushion frame provided between the side cushion frames and having a first side fixed to the first side cushion frame; and a support guide device connected between a second side of the center cushion frame and the second side cushion frame, and configured to guide a sliding movement of each of the second side cushion frame and the center cushion frame while supporting weights of the second side cushion frame and the center cushion frame.

Combination structure of seat cushion frame

The present disclosure relates to an apparatus and method for cleaning a chamber, and more particularly, to an apparatus and method for cleaning a chamber, which are capable of cleaning the chamber which is contaminated while depositing a thin film on a substrate. The chamber cleaning method in accordance with an exemplary embodiment is a method for cleaning a chamber configured to deposit a zinc oxide, the method comprising: supplying a chlorine (Cl)-containing gas and a hydrogen (H)-containing gas into a chamber; activating and reacting the separately supplied gases with each other inside the chamber to generate a reaction gas; and firstly cleaning the chamber with the reaction gas.

Chamber cleaning device and chamber cleaning method

A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.

Semiconductor device

Semiconductor device for compensating offset of sense amplifier

A refrigerator includes a main body, a door rotatably coupled to the main body, a first ice making compartment configured to generate and store ice and provided in the main body, a second ice making compartment configured to crush ice and provided in the door, and a transfer device provided to transfer the ice in the first ice making compartment to the second ice making compartment. Therefore, a structure of an ice bucket storing ice is simplified, and an ice making system is easily constructed.

Refrigerator

In an ice maker according to the present disclosure, transporter configured to supply ice to a dispenser, at least a part of which is located above an ice bucket located in the middle of the main body, may transport the ice upward to help the user take the ice conveniently even with the ice bucket located in the middle of the main body. So a refrigerator including the ice maker, according to the present disclosure, includes a storeroom to store groceries with increased utilization of the storeroom.

Ice maker and refrigerator having the same

Growing community of inventors

Gwangju-si, South Korea

Jae Jin Lee