Samsung Electronics Co., Ltd.

Jae-il Lee

Chul-woong Jang

Jun-Ho Lee

Min-Kyung Kim

Sung-Yeol Kim

Ki-Sang Kang

In-ho Choi

Do-young Kam

Ju-il Kang

Woon-sup Choi

In-su Yang

Ho-sun Yoo

Hyun-seop Shim

Seung-ho Jang

Seong-goo Kang

Jeong-gun Lee

Young-Sun Lee

Young-jin Lee

Tae-Soo Lee

Jong-won Han

Ki-jae Song

Yeon-jeong Kim

Hun-Kyo Seo

Kyung-yeon Han

Jong-pill Park

Min-sung Kim

Jong-Pil Park

Jeong-Gon Lee

Young-ki Kwak

Moon Sone

Hye-young Suh

Yoon-aa Choi

Seung-jun Chee

Jung-wook Lee

Seon-hui Shim

A protein complex including at least two monoclonal antibodies is provided. By using the protein complex, a system for simultaneously targeting at least two antigens is effectively constructed.

Protein complex and method of preparing same

A protein complex comprising (i) a first fusion protein comprising (a) a first polypeptide that comprises a first antigen-binding site and (b) a first binding protein linked to a terminus of the first polypeptide; and (ii) a second fusion protein comprising (a) a second polypeptide that comprises a second antigen-binding site and (b) a second binding protein linked to a terminus of the second polypeptide, wherein the protein complex comprises an amino acid sequence that enables cleavage between the first polypeptide and the first binding protein, and/or between the second polypeptide and the second binding protein, as well as a method for preparing a bi-specific antibody and related methods and compositions.

Protein complexes and methods of manufacturing bispecific antibodies using the protein complexes

Provided is a method of screening a target-specific antibody for an antigen that undergoes structural change in a particular physiological condition.

Method of screening antibodies with high antigen selectivity

The invention provides a fusion protein comprising (a) a first protein comprising a polypeptide which specifically binds to Annexin A1 and (b) a second protein comprising a polypeptide which induces a cytotoxic activity of a cytotoxic lymphocyte, pharmaceutical compositions comprising the fusion protein, and methods of treating or preventing cancer by administering the pharmaceutical compositions.

Pharmaceutical composition for preventing or treating cancer

A polypeptide linker comprising an antibody-binding region and an enzyme cleavage region, and related compositions, kits, and methods of using same.

Polypeptide linker and method of analyzing target material using the same

A fusion protein that includes a polypeptide binding specifically to a constant region of an antibody and a stabilization protein linked to a terminus of the polypeptide, a polynucleotide encoding the fusion protein, a cell including the polynucleotide, a method of preparing the fusion protein, and a method of isolating an antibody by using the fusion protein.

Fusion protein binding specifically to constant region of antibody, method of preparing the fusion protein, and method of isolating antibody using the fusion protein

A protein complex comprising an in vitro stabilization protein, a membrane translocation sequence domain, a biologically active molecule, and an in vivo stabilization protein, as well as methods for the use and production thereof.

Protein complex for intracellular delivery and uses thereof

Provided are a nonvolatile memory device and a read method of the same. The read method applying one of a plurality of unselected read voltages to unselected wordlines adjacent to a selected word line. The voltage applied to the unselected word lines being based on which of a plurality of selected read voltages is applied to the selected wordline.

Nonvolatile memory device capable of reducing read disturbance and read method thereof

A connecting unit to test a semiconductor chip and an apparatus to test the semiconductor chip having the same include a plurality of connectors, on which a semiconductor chip having a certain pattern of electrical connection terminals, having a plurality of holes, cables configured to electrically connect the electrical connection terminals to the exterior, and coupling units configured to selectively electrically connect the cables to the electrical connection terminals through the holes. Therefore, it is possible to perform electrical tests of semiconductor chips having various patterns of electrical connection terminals and receive the semiconductor chips in a tray at a time.

Connecting unit to test semiconductor chips and apparatus to test semiconductor chips having the same

A signal capture system for capturing a signal and storing the captured signal in a storage apparatus in real time, and a test apparatus including the signal capture system. The signal capture system includes a printed circuit board; a socket that is connected to the printed circuit board and on which a reference memory component is mounted; and an interposer that is mounted on the printed circuit board, is connected to the socket, an external apparatus, and a storage apparatus, receives first signals from the reference memory component and transmits the received first signals to the external apparatus and the storage apparatus, and receives second signals from the external apparatus and transmits the received second signals to the reference memory component and the storage apparatus, wherein a shape of the socket is defined according to a type of the reference memory component.

Signal capture system and test apparatus including the same

A field mounting-type test apparatus and method for enhancing competitiveness of a product by simulating various test conditions including a mounting environment for improving quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment thus reducing testing time and cost. The field mounting-type test apparatus includes a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT using the logic data.

Field mounting-type test apparatus and method for testing memory component or module in actual PC environment

A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

Multifunctional handler system for electrical testing of semiconductor devices

Automatic test equipment is capable of performing a high-speed test of semiconductor devices, with a low cost and high efficiency. The automatic test equipment (ATE) comprises: an ATE body configured to electrically test semiconductor devices; a field programmable gate array (FPGA) controlling drivers and comparators on the ATE; an accelerator connected to an output terminal of the FPGA and that doubles an operating frequency of the FPGA; and a decelerator connected to an output terminal of the FPGA and that converts an operating frequency of data transferred from the semiconductor device to the operating frequency of the FPGA.

Automatic test equipment capable of high speed test

A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

Growing community of inventors

Yongin-si, South Korea

Jae-il Lee