Hynix Semiconductor Inc.

Skhynix Inc.

Samsung Medison Co., Ltd.

Jae-Il Kim

Chang-Ho Do

Jae-Hyuk Im

Sang-Ah Hyun

Jun-Gi Choi

Hwang Hur

Jin-Il Chung

Jong-Sam Kim

Ga-Ram Park

Min-Su Park

No-Guen Joo

Tae-Kyun Kim

Hyoung-Jun Na

Hee-Seong Kim

Yong-Ju Kim

Taek-Sang Song

Dae-Han Kwon

Seok-Cheol Yoon

Heat-Bit Park

Bo-Yeun Kim

Won-Chul Bang

Yu-Ri Lim

Youk-Hee Kim

Ji-won Ryu

Do-Hong Kim

Kyoung-Chul Jang

Jung-woo Chang

Young-Taek Oh

Kyong-Joon Lee

Ja-Yeon Jeong

A memory device may include a plurality of memory cells; a refresh counter suitable for generating a refresh address; an address storage circuit suitable for storing an additional refresh address; an error detection unit suitable for detecting an error of selected memory cells of the plurality of memory cells in response to a refresh command in a detection period; and a refresh control unit suitable for refreshing memory cells corresponding to the refresh address or the additional refresh address among the memory cells in response to the refresh command, and controlling the refreshing of the memory cells to be delayed in the detection period.

Memory device for detecting failure of memory cells and refreshing memory cells

A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.

Memory device and operating method thereof

A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

Comparing twice-read memory cell data for error detection in a memory device

A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted to the plurality of first input pins, and determining the parity check result as a pass or fail; and one or more registers suitable for storing the inputted command/address signals when the parity check result is determined as the fail, wherein during a test operation, the number of signals having a first logic value among the command/address signals inputted to the plurality of first input pins does not correspond to the logic value of a parity bit.

Semiconductor system and method for testing semiconductor device

A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.

Memory device

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

Nonvolatile memory circuit and memory device including same

A memory device includes a plurality of memory cells for storing data; a plurality of memory cells for storing data; a non-volatile memory unit; a test control unit suitable for detecting weak memory cells among the plurality of memory cells; a program control unit suitable for controlling addresses of the detected weak memory cells to be programmed in the non-volatile memory unit; and a refresh control unit suitable for refreshing the addresses stored in the non-volatile memory unit more frequently than other memory cells.

A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.

Address storage circuit and memory and memory system including the same

A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.

Memory device and method of refreshing the same

A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

Memory device and memory system including the same

A semiconductor device includes a 1st controller suitable for generating refresh control signals for controlling at least two types of refresh operations according to an external refresh signal; and a 2nd controller suitable for controlling the at least two types of refresh operations to be evenly and alternately performed on a plurality of word lines according to the refresh control signals, a predetermined number of times during a unit refresh period corresponding to the external refresh signal.

Semiconductor device performing different types of refresh operations and method of driving the same

A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.

Semiconductor memory device

A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks each including a plurality of word lines, and one or more measurement blocks corresponding to the memory banks, respectively, and suitable for measuring an active period of an activated word line in a corresponding memory bank among the memory banks, wherein each of the measurement blocks measures the active period of the activated word line based on a first value of the code at an activation starting point of the corresponding memory bank and a current value of the code.

Memory device with advanced refresh scheme

A semiconductor system includes a semiconductor device comprising: a plurality of first input pins suitable for receiving a plurality of command/address signals; a plurality of multi-purpose registers; and a parity check unit suitable for determining a parity check result as a pass when the number of first logic values in the command/address signals corresponds to a logic value of a parity bit, determining the parity check result as a fail when the number of the first logic values does not correspond to the logic value of the parity bit, and controlling the command/address signals to be stored in the multi-purpose registers; and a function test device suitable for applying the command/address signals to the first input pins during a function test, and controlling the command/address signals such that the number of the first logic values does not correspond to the logic value of the parity bit.

A semiconductor apparatus includes a clock division block suitable for generating a first internal clock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal.

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Gyeonggi-do, South Korea

Jae-Il Kim