Seagate Technology Incorporated

Jae Ik Song

Dong Hyuck Shin

Junghwan Shin

Eun Yeong Hong

Xiong Liu

Brian Thomas Edgar

Jin Quan Shen

Hye Jeong Nam

Daniel Suhwan Kim

Jun Cheol Kim

A data storage system can connect a cache memory to a caching module, a host, and a data storage device. The caching module can employ one or more local controllers to generate a caching strategy in response to detected data storage operations and execute the caching strategy to divide the cache memory into a first pool having a first size and a second pool having a second size.

Data storage system with adaptive cache management

Systems and methods for forward corrupted track detection and by-pass are described. In one embodiment, a storage system comprising a storage controller performs a read operation for a target track of a shingled magnetic recording (SMR) disk drive and detects a read operation failure of the read operation for the target track. The storage controller also performs a boundary track read operation on one or more tracks including or adjacent to the target track and detect a forward corruption area based on the boundary track read operation. In another embodiment, a method is provided that includes detecting a read operation failure of a read operation for a track of a disk drive and performing a boundary track read operation on one or more tracks including or adjacent to the target track. The method also includes detecting a forward corruption area based on the boundary track read operation.

Forward corrupted track detection and by-pass for shingled magnetic recording drives

Implementations disclosed herein provide for sequential readback of program data in from a cached data region of a storage device. In particular, the disclosed technology provides for storing a sequence of logical addresses associated with execution of a program, the sequence of logical addresses including at least two consecutive logical addresses associated with non-consecutive data blocks in a user data region; writing data corresponding to the at least two consecutive logical addresses to sequential data blocks in a cached data region; determining that a sequence of read commands from a host computer is associated with the data; and reading the data from the cached data region.

Cache data management for program execution

Implementations disclosed herein provide systems and methods for data write management in a storage device responsive to detection of a disturbance. Responsive to the detection of the disturbance, a write operation is paused and a transducer head is moved from a first position on the target data track to a second position separated from the first position by at least one data track. At the second position, the write operation is resumed.

Data write management

Methods and devices for managing address mapping information may include writing address mapping recovery information on a user data area of a storage medium in an initially set size unit, the address mapping recovery information being generated in response to a write operation, storing the address mapping recovery information without being written on the storage medium in a non-volatile memory device when an abnormal power off occurs in a storage device, and updating the address mapping information related to the storage device based on the address mapping recovery information stored in the non-volatile memory device and the storage medium when power is applied to the storage device.

Method for managing address mapping information and storage device applying the same

Methods and apparatuses for contiguous data address management are provided. In one embodiment, an apparatus may comprise a processor configured to receive a write command including data to be written to a plurality of logical block addresses (LBAs); determine if the plurality of LBAs includes LBAs from a plurality of logical bands; and when the plurality of LBAs includes LBAs from a plurality of logical bands, combine the plurality of logical bands into a single logical band and write the data to the single logical band. In another embodiment, the processor may be further configured to separate the single logical band into the plurality of logical bands when the data written to the plurality of LBAs becomes invalid.

Method and apparatus for contiguous data address management

Methods and apparatuses for managing read or write errors are disclosed. In one embodiment, a method may comprise receiving a command to perform an operation associated with first data and a first address of a data storage medium, performing the operation at the first address, retrying the operation when the operation did not complete successfully, and storing the first data to a second address when a first threshold is exceeded. In another embodiment, an apparatus may comprise a processor configured to: receive a command to perform an operation associated with first data and a first address of a data storage medium, perform the operation at the first address, retry the operation when the operation did not complete successfully, and store the first data to a second address when a first threshold is exceeded.

Growing community of inventors

Gyeonggi-do, South Korea

Jae Ik Song