Magnachip Semiconductor, Inc.

Jae Hyung Jang

Jin Yeong Son

Hee Hwan Ji

Young Bae Kim

Kwang Il Kim

Jun Hyun Kim

In Sik Jung

Yu Shin Ryu

Hee Baeg An

Seong Woo Lee

A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.

Semiconductor device having low Rdson and manufacturing method thereof

A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.

Integrated semiconductor device and method for manufacturing the same

Semiconductor device having low Rand manufacturing method thereof

A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.

Semiconductor device structure having low Rdson and manufacturing method thereof

A Hall sensor with improved doping profile is disclosed. The Hall sensor includes a semiconductor substrate, a sensing region formed on the substrate, an isolation region formed on the sensing region, and a high concentration doping region formed on an upper portion of the sensing region.

Hall sensor with improved doping profile

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Daejeon, South Korea

Jae Hyung Jang