Samsung Electronics Co., Ltd.

Jae-hyun Yoo

Jin-Hyun Noh

Jong-Sung Jeon

Yong-Woo Jeon

Kwan-young Kim

Kee-Moon Chun

Byeong-Ryeol Lee

Su-Tae Kim

Woo-Yeol Maeng

Seong-Hun Jang

Jae-Ho Kim

Ui-hui Kwon

Ui Hui Kwon

Myoung-Kyu Park

Kang-hyun Baek

Young-Mok Kim

Kyu Ok Lee

Kwan-Jae Song

Da-won Jeong

Hiroki Fujii

Jun-hyeok Kim

Jun Hyeok Kim

Yong Woo Jeon

Da Won Jeong

In-Hack Lee

Kyu-ok Lee

A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

Semiconductor device

A semiconductor device includes a semiconductor substrate including an active region defined in a well impurity layer having a first conductivity type, a gate electrode on the active region, and a gate insulating layer between the gate electrode and the active region. The active region includes a source region and a drain region at sides of the gate electrode, the source region and the drain region having a second conductivity type, a channel region between the source and drain regions, the channel region having the first conductivity type, a first halo region in contact with the source region and a second halo region in contact with the drain region, the first halo region and the second halo region having the first conductivity type, and a slit well region between the first and second halo regions, the slit well region having the first conductivity type.

Semiconductor device and display driver IC using the same

A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Power device

A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.

Semiconductor device having a drift region with non-uniform impurity concentration profile

A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

Semiconductor device and method of manufacturing the same

According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.

Semiconductor device using three dimensional channel

Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

Semiconductor devices

Provided are semiconductor devices. A semiconductor device includes a first well formed in a substrate; an element isolation layer formed on the first well; a second well formed in the first well on a first side of the element isolation layer; a third well formed in the second well, the third well has a higher concentration of impurities than the second well; a first electrode electrically connected to the third well; a fourth well formed in the first well on a second side of the element isolation layer; a fifth well formed in the fourth well, the fifth well has a different conductivity type from the fourth well; a second electrode electrically connected to the fifth well; and a sixth well overlapping the fourth well, the sixth well has a lower concentration of impurities than the fourth well.

A semiconductor device including an electrostatic discharge (ESD) protection circuit includes an input port, a logic circuit receiving an input signal applied to the input port and generating an output signal based on the input signal, and an ESD protection circuit adjusting a level of the input signal when the level of the input signal exceeds a predetermined range. The ESD protection circuit includes a first fin and a second fin arranged on a semiconductor substrate in parallel, and a gate electrode formed in a direction crossing the first fin and the second fin, each of the first fin and the second fin includes a source region, a drain region, and a channel region disposed between the source region and the drain region, the channel region is disposed under the gate electrode, a source region of the first fin and a drain region of the second fin are disposed at a first side of the gate electrode, and a drain region of the first fin and a source region of the second fin are disposed at a second side of the gate electrode.

Semiconductor device including ESD protection circuit

A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

An electrostatic discharge (ESD) protection circuit includes a substrate, a semiconductor layer provided on the substrate to have a first conductivity type, a first well provided in a first region of the semiconductor layer to have a second conductivity type, an insulating pattern provided in the first well to cross the first well, and first and second doped regions provided in an upper portion of the first well to have the first conductivity type. The first and second doped regions may be laterally spaced apart from each other with the insulating pattern interposed therebetween.

Electrostatic discharge protection circuit

Provided are an electrostatic discharge (ESD) protection device having a high-resistance region and a method of forming the same. The device includes a well on a substrate. A first impurity region is formed on the well and connected to an input/output pad. A second impurity region is formed on the well, spaced apart from the first impurity region, and connected to a ground (Vss). A third impurity region is formed on the well, spaced apart from the first impurity region, and connected to the ground (Vss). An isolation layer is formed between the first impurity region and the second impurity region. A high-resistance region, which directly contacts the first impurity region and the well and has a resistance higher than the first impurity region, is formed between the first impurity region and the isolation layer. The well and the third impurity region include first conductive type impurities. The first impurity region and the second impurity region include second conductive type impurities different from the first conductive type impurities.

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Suwon-si, South Korea

Jae-hyun Yoo