Samsung Electronics Co., Ltd.

Jae-hyun Phee

Ho-jin Lee

Jung-Hwan Kim

Ju-Il Choi

Tae Hong Min

Kyu-ha Lee

Hyun-Soo Chung

Chajea Jo

Jeong-Woo Park

Ho-Geon Song

Se-Young Jeong

Sang-Sick Park

Son-kwan Hwang

Chang-Seong Jeon

Uihyoung Lee

Seyoung Jeong

Ha-Young Yim

Uihyouong Lee

Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Methods of forming a semiconductor package using a seed layer and semiconductor packages formed using the same

A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

Semiconductor chip having via electrodes and stacked semiconductor chips interconnected by the via electrodes

A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Semiconductor apparatus, method of manufacturing the same, and method of manufacturing semiconductor package

A semiconductor device includes a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion and supports the protruding portion.

Semiconductor devices having electrodes

A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.

Semiconductor device having through silicon via (TSV)

Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate. The stacked insulation layer can include at least one first insulation layer and at least one second insulation layer whose dielectric constant is different than that of the first insulation layer. One insulation layer may be a polymer and one insulation layer may be a silicon based insulation layer. The insulation layers may be uniform in thickness or may vary as a distance from the substrate changes.

Multi-layer TSV insulation and methods of fabricating the same

A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.

Growing community of inventors

Incheon, South Korea

Jae-hyun Phee