Samsung Electronics Co., Ltd.

Jae-Hyun Joo

Wan-Don Kim

Cha-young Yoo

Yong-Kuk Jeong

Wan-don Kim

Seok-Jun Won

Hideki Horii

Eun-ae Chung

Doo-sup Hwang

Soon-yeon Park

Seok-jun Won

A method of forming a multi-layered thin film uses photolysis chemical vapor deposition (PCVD). In the method, a substrate for a process of forming the multi-layered thin film is prepared. At least two source gases are supplied to the substrate. Reaction lights having particular wavelengths are prepared, which are absorbed by each of the source gases, are prepared. The reaction lights having particular wavelengths are alternatingly emitted on the substrate to a form a predetermined multi-layered thin film. A photolysis chemical vapor deposition (PCVD) reactor is disclosed, having a chamber with a substrate support, a gas supply system for supplying a plurality of source gases to the substrate in the chamber, and a light supply system mounted at one side of the chamber. The light supply system selectively emits one of the plurality of reaction lights having different wavelengths on the substrate.

Method of fabricating a multi-layered thin film by using photolysis chemical vapor deposition

A phase changeable memory device includes a lower interlayer dielectric layer on a semiconductor substrate. A plurality of first phase changeable data storage elements is disposed on the lower interlayer dielectric layer. A middle interlayer dielectric layer covers the first phase changeable data storage elements and the lower interlayer dielectric layer. A plurality of second phase changeable data storage elements is disposed on the middle interlayer dielectric layer. The first and second phase changeable data storage elements are arrayed in rows and columns such that respective first phase changeable data storage elements are disposed between respective adjacent second phase changeable data storage elements in the rows and columns. A plate electrode overlies the first and second phase changeable data storage elements and is electrically connected to the first and second phase changeable data storage elements. Related fabrication methods are also disclosed.

Phase changeable memory devices having multi-level data storage elements and methods of fabricating the same

A fabrication method for forming a semiconductor device having a MIM (Metal-Insulator-Metal) capacitor is provided. A lower electrode is formed on a substrate. The lower electrode is subjected to a pre-annealing. The pre-annealing includes a thermal annealing in a hydrogen atmosphere, a nitrogen atmosphere or a mixed atmosphere of hydrogen and nitrogen. A capacitor dielectric layer is formed on the lower electrode. An upper electrode is formed on the capacitor dielectric layer. According to the present invention, the characteristic of a MIM capacitor can be enhanced by the pre-annealing without any substantial change in the materiality of the lower electrode.

Method and manufacturing a semiconductor device having a metal-insulator-metal capacitor

Methods for forming a stacked capacitor include forming a first dielectric layer having a contact plug therein on an integrated circuit substrate. A second dielectric layer including a storage node hole is formed adjacent the contact plug on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer has an associated work function. The conductive layer is oxidized to form a conductive oxide layer on the conductive layer. The conductive oxide layer has an associated work function that is sufficiently close to the work function of the conductive layer that the conductive layer and the conductive oxide layer operate together as the node of the stacked capacitor. The second dielectric layer is removed to define the node of the stacked capacitor. The stacked capacitor may be a metal-insulator-metal (MIM) capacitor and the conductive layer may be formed of a material selected from the group consisting of ruthenium (Ru), tungsten (W) and iridium (Ir). Related structures (devices) are also disclosed.

Methods for manufacturing storage nodes of stacked capacitors

In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor

A method for manufacturing a capacitor of a semiconductor memory device by controlling thermal budgets is provided. In the method for manufacturing a capacitor of a semiconductor memory device, a lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.

Method for manufacturing capacitor of semiconductor memory device controlling thermal budget

A method of fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device having an upper and lower electrode formed of metal is provided. Portions of a conductive layer for a lower electrode on inner walls of holes are not removed. Portions of the conductive layer for a lower electrode outside the holes are selectively etched back and node-separated.

Method of fabricating a MIM capacitor using etchback

MRAM cells include a magnetic resistor having first and second terminals, and access transistor that is connected to the first terminal, and a bit line that also is connected to the first terminal. A reading word line is connected to the second terminal, and a word line is connected to the access transistor. The first terminal may include a conductive axis and the magnetic resistor at least partially surrounds the conductive axis. The MRAM cell may be written by turning on the access transistor to force writing current into the first terminal, and thereby change the resistance of the magnetic resistor. Reading may be performed by applying voltage between the bit line and the reading word line, and sensing current through the magnetic resistor in response.

Magnetic random access memory (MRAM) cells including an access transistor and a bit line that are connected to a terminal of a magnetic resistor, and methods of operating same

Methods are provided for manufacturing an integrated circuit device in which a metal layer is formed on an integrated circuit substrate. A capping layer is formed on the metal layer opposite the integrated circuit substrate. The metal layer covered with the capping layer is heat-treated. The capping layer is removed and the metal layer, which is exposed by removal of the capping layer, is plasma-treated.

Methods for manufacturing semiconductor devices having a metal layer

The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

Methods for manufacturing integrated circuit metal-insulator-metal capacitors including hemispherical grain lumps

Methods for manufacturing a node of a stacked capacitor are provided. A first dielectric layer having a contact plug therein is formed on an integrated circuit substrate. A second dielectric layer including a storage node hole adjacent the contact plug is formed on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer on the second dielectric layer is removed to provide a conductive storage node in the storage node hole. After the conductive layer on the second dielectric layer is removed, the conductive storage node is heat treated to reflow the conductive storage node before additional layers are formed on the conductive storage node.

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Seoul, South Korea

Jae-Hyun Joo