Samsung Electronics Co., Ltd.

Jae-Hyok Ko

Han-Gu Kim

Ki-Tae Lee

Jin Seong Heo

Jong-Kyu Song

Sung-pil Jang

Min-Chang Ko

Woo-sub Kim

Suk-jin Kim

Kyoung-sei Choi

Kyong-Soon Cho

Kwan-Jai Lee

Keung-beum Kim

Chang-Su Kim

Kyoung-Ki Jeon

Il-Hun Son

Suk-Jin Kim

Kyoung-Sik Im

Hyo-Cheol Ban

An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

Electrostatic discharge protection device and electronic device having the same

In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Semiconductor chip package

An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode.

Electrostatic discharge protection element and electrostatic discharge protection circuit including the same

A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.

Semiconductor chips having improved electrostatic discharge protection circuit arrangement

There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VESD protection element connected between an I/O pad and a Vline, a ground voltage (V) ESD protection element connected between the I/O pad and a Vline, and a power clamp element connected between the Vline and the Vline, and wherein the VESD protection element, the power clamp element, and the VESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

Integrated circuit device having input/output electrostatic discharge protection cell equipped with electrostatic discharge protection element and power clamp

A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.

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Hwaseong-si, South Korea

Jae-Hyok Ko