Sony Corporation

Sony Electronics Inc

Gsi Technology, Inc.

Skhynix Inc.

Jae-Hyeong Kim

Patrick Chuang

Yu-Chi Cheng

Amal Akbar

Mu-Hsiang Huang

Chih Tseng

Hsin-Ley Suzanne Chen

Chih-Chiang Tseng

Chungji Lu

A data output device includes: a plurality of storage devices coupled in parallel to store input data, and having a storage region with a predetermined depth; and a selector suitable for selecting an output of any one storage device among the plurality of storage devices.

Serializer and memory device including the same

A data output device includes: a first serializer suitable for receiving first parallel data having a first size from a first data line, and selectively outputting first and second serial data each having a second size corresponding to &#xbd; of the first size; a second serializer suitable for receiving second parallel data having the first size from a second data line, and selectively outputting third and fourth serial data each having the second size; and a latch circuit suitable for latching the output of the first serializer and the output of the second serializer, and outputting serial output data having the first size.

Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry

A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may be coupled to an output of the second inverter on a first terminal and a ground on a second terminal, wherein the ground is also coupled to a pull-down element of the main output buffer.

Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features

The system described herein provides a minimized skew generator that has very small timing variation. Four phase signals are compressed into one signal including the four phase information. Therefore, the signal with all of the phase information travels on the same line, thus avoiding the concerns of skewing based on different sizes of metal lines. Since there are two rising edges and two falling edges within one signal, an enable line is utilized to select between the first and second, rising and falling edges. With this processing, the system has only one critical signal output, thus requiring only one signal line. Skewing of the signals and the amount of power required are both reduced.

Minimized line skew generator

An integrated circuit comprises a double frequency clock generator and a double input generator to test semiconductor devices at frill frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock and test data signals at a normal (1&#xd7; mode) and high-speed rate (2&#xd7; mode) to a device under test. In 1&#xd7; mode, clock generator and test data generator circuits pass through the differential clock signals and test data values provided by a testing device unchanged. In 2&#xd7; mode, the clock generator circuit receives the differential clock signal as clock signals clk and clkb and outputs clock signals clk_int and clkb_int that are inverted signals and twice the frequency of clk and clkb. The test data generator circuit clocks test data values into registers according to clk_int and clkb_int to generate an increased number of test data values per clock signal clk.

Test semiconductor device in full frequency with half frequency tester

A dynamic sense amplifier for static random access memory (SRAM) is provided. The dynamic sense amplifier includes a pre-amplifier configured to amplify small input signals according to a first clock signal, and a main sense-latch coupled to the pre-amplifier, wherein the main sense-latch is configured to respond to the small input signals according to a second clock signal and a third clock signal, and wherein the dynamic sense amplifier is configured to consume substantially zero direct current power.

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San Ramon, CA, United States of America

Jae-Hyeong Kim