Skhynix Inc.

Jae Hyeon Shin

In Gon Yang

Sungmook Lim

Hyung Jin Choi

Tae Ho Kim

Sung Hyun Hwang

Sung Hun Kim

Gwi Han Ko

Hyun Soo Lee

Nam Kyeong Kim

Gil Bok Choi

Dae Hwan Yun

Sung Dae Choi

Gwan Park

Chang Han Son

The present technology relates to an electronic device. A memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.

Memory device and method of operating the memory device

Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

Semiconductor memory device with high electron mobility channels and method of manufacturing the same

A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.

Page buffer, memory device including the page buffer and operating method thereof

A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.

Memory device and operating method of the memory device

A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.

Memory device and operating method thereof

The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.

A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.

Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.

Semiconductor memory device and method of operating the same

A memory device and method of operating the same. A memory device includes a memory block, a peripheral circuit, and a program operation controller. The memory block includes a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and each of the first sub block and the second sub block is connected to a plurality of word lines and a common source line. The program operation controller controls the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or a plurality of bit lines connected the memory block, and to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points in the step of precharging the channel region.

Memory device and method of operating the same

A memory device having improved read reliability includes: first blocks coupled to a first global line group and second blocks coupled to a second global line group; a voltage generator configured to generate an operating voltage for an operation performed on the first blocks and the second blocks; a block decoder configured to generate a block select signal for selecting a memory block on which a main operation is to be performed from among the first blocks as a selected block; and a block voltage controller configured to control the block decoder and the voltage generator to: perform a channel initializing operation of discharging channel regions of the selected block and a shared block which is selected from among the second blocks according to the block select signal; and perform a word line floating operation on the selected block and the shared block after the channel initializing operation.

A method of operating a memory device, the method including matching a voltage of a selected word line, among word lines coupled to the plurality of memory cells, with a voltage of unselected word lines. The method including precharging a channel region of the plurality of memory cell strings through the common source line while discharging the selected word line and the unselected word lines.

A semiconductor memory device includes a memory cell array coupled to a plurality of word lines, a voltage generator generating a program voltage and first and second pass voltages in response to voltage generation control signals, an address decoder selectively applying the program voltage and the first and second pass voltages to the plurality of word lines in response to address decoder control signals, and a control logic controlling the voltage generator and the address decoder to perform a program operation.

Semiconductor memory device and operating method thereof

A semiconductor device and a method of operating the same are provided. The semiconductor device includes a memory block including a plurality of pages having a plurality of first cells and a plurality of second cells, a circuit group configured to read first cells and second cells of a selected page of the pages a strobe signal control circuit configured to store source bouncing information generated during a read operation of the first cells of the selected page and output a strobe signal based on stored information, and a control circuit configured to control the circuit group in response to the strobe signal during a read operation of the second cells of the selected page.

Growing community of inventors

Gyeonggi-do, South Korea

Jae Hyeon Shin