Skhynix Inc.

Seoul National University

Jae Hyeok Yang

Ji Hyo Kang

Gang Sik Lee

Kyung Hoon Kim

Joo Hyung Chae

Sang Yeon Byeon

Dong Hyun Kim

Suhwan Kim

Dae Han Kwon

Gi Moon Hong

Kyu Bong Kong

Shin Hyun Jeong

A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.

Clock distribution circuit and semiconductor apparatus including the same preliminary class

Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Clock distribution circuit and semiconductor apparatus including the same

A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

Semiconductor device for controlling voltage at an input node of a circuit during a low power mode

A semiconductor apparatus includes a voltage divider, a plurality of reference voltage controllers, and a plurality of receivers. The voltage divider outputs a plurality of division voltages. Each of the plurality of reference voltage controllers is configured to receive in common the plurality of division voltages. Each of the plurality of receivers is configured to receive data by utilizing at least one reference voltage. The plurality of reference voltage controllers are coupled to the plurality of receivers in a one-to-one manner, and each of the plurality of reference voltage controllers is configured to select at least one division voltage among the plurality of division voltages and provide the one division voltage as the at least one reference voltage to a corresponding receiver among the plurality of receivers.

Semiconductor apparatus for generating a reference voltage

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Icheon-si, South Korea

Jae Hyeok Yang