Skhynix Inc.

Jae Hwan Seo

Chul Moon Jung

Sung Soo Chi

Woo Yeol Shin

A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.

Fuse latch of semiconductor device for latching data of a repair fuse cell

A semiconductor device is disclosed. The semiconductor device includes a first cell array and a second cell array, a first main word line disposed over the first cell array, a second main word line disposed over the second cell array, and a row decoder block disposed between the first cell array and the second cell array, and configured to include a common signal line that is commonly coupled to the first main word line and the second main word line such that a main word line control signal is simultaneously supplied to the first main word line and the second main word line.

Semiconductor device

A semiconductor device is disclosed, which is configured to perform a test using various conditions during a test mode. The semiconductor device includes a voltage generation circuit configured to output 2(n is an integer of n&#x2265;2) bit-line precharge voltages through different power-supply lines, based on a mode control signal, and a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2bit-line precharge voltages to corresponding bit lines in units of 2successive bit-lines within the same cell array.

An interposer for inspecting reliability of a semiconductor chip is disclosed. The interposer for inspection includes: at least one active pad disposed in an active region of a first surface, and including: pads through which data and a control signal for testing an inspection target chip are received (input) and sent (output) during an active mode; and pads for receiving a power-supply voltage needed to operate the inspection target chip and the interposer during the active mode; at least one passive pad disposed in a passive region of the first surface, and including: pads receiving data for testing the inspection target chip during a passive mode, and a power-supply voltage needed to operate the inspection target chip and the interposer during the passive mode; and at least one bump pad disposed over a second surface facing the first surface, and to be coupled to the inspection target chip.

Growing community of inventors

Icheon-si, South Korea

Jae Hwan Seo