Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Chung Ang University Industry Academic Cooperation

Industry-university Cooperation Foundation

Zaram Technology Co., Ltd.

G.clo Inc.

Jae-Hun Jung

Tae-Whan Kim

Hye-Seung Yu

Won-il Park

Jung-Min Lee

Kwang-Hyun Baek

Sukyong Kang

Hong Chang Yeoh

Dong-Ick Son

Yun-Hwan Jung

Young-Ho Kim

Hyunui Lee

Joon Hyun Baek

Hee-Yeon Yang

Wonjoo Yun

Jae-Ho Kim

Hun-Dae Choi

Hangi Jung

Won-Joo Yun

SukYong Kang

Wangsoo Kim

Yoo-Chang Sung

Tae-won Son

Chong-seung Yoon

Hyung-jin Son

Joo-Hyung You

Jae-Won Shin

Fushan Li

Jeong-Yong Lee

Sung-Keun Lim

Mun-Seop Song

Jae-Ho Shim

Jae-Seok Yi

Hyun-Ui Lee

Sung-Oh Ahn

Cheongryong Cho

Kiduk Park

A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Memory device including parity error detection circuit

An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

Electronic circuits for outputting post emphasis signals

A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.

Delay circuit of a semiconductor memory device, a semiconductor memory device and a method of operating the same

An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

Input-output circuit for supporting multiple-input shift register (MISR) function and memory device including the same

A solar cell using a p-i-n nanowire that may generate light by absorbing solar light in a wide wavelength region efficiently without generating light loss and may be manufactured with a simplified process and low cost. The solar cell includes: a semiconductor layer formed of a semiconductor material; and a photoelectromotive layer including a semiconductor structure including a core-nanowire that extends long in an upward direction of the semiconductor layer and is formed of an intrinsic semiconductor material, and a shell-nanowire that is formed to surround a periphery of the core-nanowire and is formed of a semiconductor material, wherein the semiconductor material that is used for forming the semiconductor layer includes an n-type semiconductor material, or the semiconductor material that is used for forming the shell-nanowire includes a p-type semiconductor material, and the semiconductor material that is used for forming the semiconductor layer includes a p-type semiconductor material, and the semiconductor material that is used for forming the shell-nanowire includes an n-type semiconductor material.

Solar cell using p-i-n nanowire

Provided are an electronic device and methods of fabricating the same, the electronic device include a device-substrate, a stacked structure, and an electrode. The stacked structure includes a graphene thin film between a first insulator and a second insulator. The electrode is disposed over the stacked structure.

Electronic device including graphene thin film and methods of fabricating the same

Example embodiments are directed to an electronic device and a method for manufacturing the same. The electronic device includes a polymer thin film and an electrode. The polymer thin film includes nanoparticles. The electrode is formed by attaching a graphene thin film of a sheet shape formed through graphene deposition using a vapor carbon supply source to the polymer thin film. In the method, a graphene thin film of a sheet shape is formed through graphene deposition using a vapor carbon supply source. A polymer solution with distributed nanoparticles is prepared. The polymer solution with distributed nanoparticles is spin-coated on a substrate. A polymer thin film comprising the nanoparticles is formed by drying the spin-coated polymer solution. An electrode is formed by attaching the graphene thin film onto the polymer thin film.

Electronic device utilizing graphene electrodes and organic/inorganic hybrid composites and method of manufacturing the electronic device

Provided are a photodetector (PD) using a graphene thin film and nanoparticles and a method of fabricating the same. The PD includes a graphene thin film having a sheet shape formed by means of a graphene deposition process using a vapor-phase carbon (C) source and a nanoparticle layer formed on the graphene thin film and patterned to define an electrode region of the graphene thin film, the nanoparticle layer being formed of nanoparticles without a matrix material. The PD has a planar structure using the graphene thin film as a channel and an electrode and using nanoparticles as a photovoltaic material (capable of forming electron-hole pairs due to photoelectron-motive force caused by ultraviolet (UV) light). Since the PD has a very simple structure, the PD may be fabricated at low cost with high productivity. Also, the PD includes the graphene thin film to reduce power consumption.

Photodetector using a graphene thin film and nanoparticles, and method for producing the same

A direct digital frequency synthesizer and a synthesizing method thereof. The direct digital frequency synthesizer uses a hybrid digital to analog converter, which matches output data of a phase accumulator to a sine wave amplitude using a hybrid DAC, including a non-linear DAC and a linear DAC. The non-linear DAC outputs a direct base point current using some bits of output data of a phase accumulator, causing the linear DAC to output a gradient current based on gradient information generated using other bits of the output data of the phase accumulator. These currents are summed for the analog output.

Direct digital frequency synthesizer using hybrid digital to analog converter and synthesizing method thereof

The present invention relates to a digital to analog converter, to a return-to-zero digital to analog converter with improved wideband characteristics by enabling a return-to-zero output without separate clock and controller, and a converting method thereof. Since the return-to-zero digital to analog converter and the converting method thereof are capable of outputting an RZ output without directly providing a clock signal to an analog circuit by configuring a switch for generating a zero point signal and a differential pipeline for providing a differential signal to control the switch according to input digital data using a differential structure, the converter can provide wideband characteristics and high dynamic performance.

Return to zero digital to analog converter and converting method thereof

The present invention relates to a direct digital frequency synthesizer using a variable sine wave-weighted digital to analog converter with improved size and efficiency and a synthesizing method thereof. The direct digital frequency synthesizer and the synthesizing method thereof are capable of simplifying a configuration for matching output data of a phase accumulator to sine wave amplitude without increase in complexity of a DAC by applying a nonlinear DAC for directly generating a current corresponding to base points with sine weights and a variable sine wave-weighted DAC for generating fine currents to be combined with variable weights based on the base points. Accordingly, it is possible to provide a high quality output, reduce a size and power consumption, and increase a speed.

Direct digital frequency synthesizer using variable sine wave-weighted digital to analog converter and synthesizing method thereof

A nonvolatile organic bistable memory device includes a substrate, a lower electrode disposed on the substrate, a lower charge injection layer disposed on the lower electrode, an insulating polymer layer including nanoparticles disposed on the lower charge injection layer, an upper charge injection layer disposed on the insulating polymer layer, and an upper electrode disposed on the upper charge injection layer. The lower and upper charge injection layers each include fullerenes and/or carbon nanotubes.

Nonvolatile organic bistable memory device and method of manufacturing the same

Provided may be a method of fabricating a flash memory device having metal nano particles. The method of manufacturing a flash memory device may include forming a metal oxide thin layer on a semiconductor substrate, forming a floating gate of an amorphous metal silicon oxide thin layer by performing a thermal treatment process on the semiconductor substrate where the metal oxide thin layer is formed, and forming metal nano particles in the floating gate by projecting an electron beam on the floating gate, the metal nano particles being surrounded by a silicon oxide layer.

Method of manufacturing a flash memory device

A flash memory device with a nanoscale floating gate and a method of manufacturing thereof are disclosed. At least one embodiment of the present invention provides a much simpler and easier method of manufacturing nanocrystals (or nanocrystallines) for the flash memory device than the conventional method. Since the nanocrystals are homogeneously dispersed as a polymer layer without agglomeration, size and density of the nanoparticles may be controlled. Additionally, one embodiment of the present invention provides memory devices with nanoscale floating gates, and related methods of manufacture, of high efficiency and cost effectiveness by employing electrically and chemically more stable nanoscale floating gates compared to conventional ones.

Flash memory device utilizing nanocrystals embedded in polymer

Growing community of inventors

Seoul, South Korea

Jae-Hun Jung